JPH04371018A - pulse delay circuit - Google Patents

Abstract

PURPOSE:To delay a pulse signal with high resolution. CONSTITUTION:A set value is given to select signal inputs 315 to 320 before a pulse to be delayed is inputted from an input 313. Propagation delay times of one-common input gates 301 and 304, two-common input gates 302 and 305, and three-common input gates 303 and 306 are S, S-a, and S-2a respectively. The difference between the extent of delay for each set value and that for the next set value is always (a), and consequently, the obtained delay resolution is shorter than the propagation delay time of a logical gate.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse delay circuit, and more particularly to a pulse delay circuit suitable for delaying pulses with high resolution.

0002

2. Description of the Related Art A conventional pulse delay circuit will be explained with reference to FIG. This conventional example is comprised of selectors 101-104 with two inputs and one output, and logic gates 111-114 connected in cascade in first, second, fourth, and eighth stages, respectively. In each of the selectors 101 to 104, when a low level logic signal (hereinafter referred to as L) is input to the select signal inputs 107 to 110, the A input side is selected,
The logical value of the A input is output to the Q output side. Conversely, when a high level logic signal (hereinafter referred to as H) is input to the select signal inputs 107 to 110, the B input side is selected and the logic value of the B input is output to the Q output side. be.

[0003] The delayed pulse is input from the input terminal 105, and prior to inputting the delayed pulse, the selectors 101 to 101 are input.
A setting value corresponding to a desired amount of delay is input to select signal inputs 107 to 110 of 104. Here, the input four-bit setting values are conveniently set (X1, X2, X3,
4). However, X1 to X4 are L or H, and X1 is the select signal input 107, X2 is the select signal input 108, and X3 is the select signal input 1.
09, X4 indicates the setting value of the select signal input 110. For example, in this example, the setting value that provides the smallest delay amount is (L, L, L, L), which is the case where low-level logic signals are input to all select signal inputs. In this case, the delayed pulse passes through the input terminal 105.
This is a path from the A input of the selectors 101 to 104 to the output terminal 106 via the Q output, and the logic gate 111
This is a route that does not pass through 114 at all. The setting value that provides the next smallest delay amount after this minimum delay amount is (H, L, L,
L), and the delayed pulse passes through only one logic gate 111 before reaching the output terminal 106. Therefore, the amount of delay obtained is larger than the minimum delay amount by the propagation delay time of one stage of logic gates. Similarly below,
As shown in Fig. 2, by changing the setting value, the passage path of the delayed pulse, that is, the number of stages through which the delayed pulse passes can be changed, and it is possible to sequentially obtain a large amount of delay. The delay resolution obtained corresponds to the propagation delay time of one stage of logic gates.

[0004] Related devices of this type include, for example, IE, Proceedings of ITC, 1989, pp. 558-5.
66 pages (IEE, PROCEEDINGS OF
ITC 1989).

[0005]

[Problems to be Solved by the Invention] In the above-mentioned conventional technology, it is not possible to make the delay resolution obtained less than the propagation delay time of one stage of logic gates provided between the selectors, and it is not possible to perform pulse delay with high resolution. The problem was that I couldn't do it.

An object of the present invention is to provide a pulse delay circuit that can perform a delay operation smaller than the propagation delay time of one stage of logic gates and obtain high delay resolution.

[0007]

[Means for solving the problem] The above problem is achieved by connecting logic gates with different propagation delay times in cascade via a signal switching circuit by changing the number of signals input simultaneously, and by changing the number of signals input simultaneously. This is achieved by switching and controlling the passage route.

[0008]

[Operation] Logic gates having different numbers of simultaneously input signals have different propagation delay times, and the signal switching circuit determines the logic gate through which the delayed pulse passes. This allows the amount of delay of the delayed pulse to be controlled.

[0009]

Embodiment An embodiment of the present invention will be described below with reference to FIGS. 3 to 6. As shown in FIG. 3, the pulse delay circuit according to the present invention is composed of two-input one-output selectors 307 to 312 and three-input OR gates 301 to 306. Among these, the selection functions regarding the input and output signals of the selectors 307 to 312 are conventional. (101 to 104 in FIG. 1). Further, the three-input OR gates 301 and 304 have a signal input to only one of the three inputs (A in the figure) (hereinafter, this gate is referred to as one common input gate), and the three-input OR gates 302 and 305 have two inputs. Input (A, B in the figure)
Signals are commonly input to three inputs (A, B, and C in the figure) 303 and 306 (the former is called a two-common input gate, and the latter is called a three-common input gate). Hereinafter, the difference in propagation delay time when the number of signals commonly input is different will be described using FIG. 4. FIG. 4 shows a configuration diagram of a general three-input OR gate. That is, in FIG. 4, when configuring one common input gate, it is connected only to the A input, when configuring two common input gates, it is connected to A and B inputs, and when configuring three common input gates, it is connected to A, B, and C inputs. , a signal is commonly input to each. When the rising edge of the delayed pulse is input to one common input gate, only the transistor 404 is turned on, and at this time, a current according to the on-resistance flows at point K, and the voltage at the output O becomes high level. Similarly, when the rising edge of the delayed pulse is input to the two common input gates and the three common input gates, the transistor 404
, 405 and transistors 404, 405, and 406 are simultaneously turned on. At this time, the on-resistance of the transistor that determines the magnitude of the current flowing through point K is 1
/2, 1/3, which is twice or three times as large as in the case of one common input gate. That is, the ratio of currents at point K in the first to third common input gates is 1:2:3. As the current at point K increases, the time for discharging the capacitance after point K, ie, the time for the voltage at point K to transition from high level to low level, becomes shorter. Therefore, the propagation delay time of the rising edge of the input pulse from each input to output O decreases as the number of common inputs increases, and the decrease can be made smaller than the propagation delay time of the logic gate. be.

The operation of a pulse delay circuit in which such logic gates having different numbers of common inputs are connected as shown in FIG. 3 will be described below. As in the conventional example, a delayed pulse is input from input 313, and prior to this, set values are given to select signal inputs 315-320. FIG. 5 shows each set value, the type of gate through which the delayed pulse passes, and the amount of delay obtained at that time. The notation method of setting values is the same as in Fig. 2, and from the left, select signals 315 to 320
It shows the value up to. Regarding the amount of delay, it is the value when the propagation delay time at the time of one common input is S, and the propagation delay time decreases by a every time the number of inputs increases by one. Therefore, the propagation delay times of one common input gate 301, 304, two common input gates 302, 305, and three common input gates 303, 306 are S, S-a, and S-2a, respectively. As is clear from FIG. 5, the difference between the amount of delay for each set value and the amount of delay for the next set value is always a, and therefore the delay resolution obtained is smaller than the propagation delay time of the logic gate. In this embodiment, six stages of three-input OR gates are connected, but the essence of the present invention is not limited by the type of logic gates or the number of stages connected.

[0011]

[Effects of the Invention] According to the present invention, by changing the number of signals simultaneously input to a logic gate, the propagation delay time of the logic gate can be changed, and by switching and using this, high resolution can be achieved. Pulse delay can be performed.

[Brief explanation of drawings]

[Figure 1] Conventional pulse delay circuit diagram,

[Fig. 2] An explanatory diagram of the operation of the conventional example,

FIG. 3 is a circuit diagram of an embodiment of the present invention;

FIG. 4 is an explanatory diagram of the operating principle of this embodiment,

FIG. 5 is an explanatory diagram of the operating principle of this embodiment.

[Explanation of symbols]

313...Delayed pulse input, 307-312...Selector circuit, 301-306...Logic gate, 315-320...
Select signal input.

Claims (1)

[Claims] 1. Circuit means for selectively switching a passage path of a pulse signal, and a logic circuit having a plurality of inputs in which the number of signals simultaneously input is different, are connected to one of the inputs of the switching circuit means. A plurality of circuits are connected in series to which a logic circuit is connected and a pulse signal is directly input to the other input without going through the logic circuit. pulse delay circuit.