JPH04372018A - High speed processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor that performs high-speed processing, such as a processor that performs pipeline processing.

0002

2. Description of the Related Art An example of a processor that performs pipeline processing is the Intel i860TM 64-bit microprocessor. i860TM pipeline processing is
i860TM 64-bit Microprocessor Advanced Information Chapter 4.0 Bus Operations
New cycles can be started until there are three outstanding cycles, as described in the section.

[0003] Therefore, if a certain cycle in the pipeline finishes processing before two subsequent cycles start, a new cycle can be started. However, if a cycle in the pipeline does not finish processing before the start of two subsequent cycles, a new cycle cannot be started, and the processor is placed in a wait state, which increases the processor's capacity. You will not be able to make full use of it.

0004

[Problems to be Solved by the Invention] In the conventional example described above, the processing time for a certain cycle during pipeline processing is long, and if the processing is not completed before the start of two cycles after that cycle, the subsequent two cycles will be delayed. No matter how fast one cycle is processed, it cannot be processed and three unprocessed cycles accumulate, making it impossible to start a new cycle.

An object of the present invention is to enable high-speed processing cycles during pipeline processing to be executed regardless of cycles that take a long processing time, and to make full use of the processor's capabilities.

[0006]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides for a cycle that can be processed at high speed among unprocessed cycles in a pipeline to be processed by a previous cycle that takes a long processing time. When a cycle cannot be completed, a cycle that can be processed at high speed can be used to complete a cycle without waiting for the previous cycle, which takes a long time, to complete.

For this reason, the processor of the present invention is provided with a wait signal for the unprocessed cycle in the pipeline, and while this wait signal is being output, it is processed without waiting for the completion of the cycle corresponding to the wait signal. This allows the subsequent cycles to be completed first.

Furthermore, in the processor of the present invention, a flag indicating whether or not to accept a wait signal is added to the instruction structure so that the above-mentioned wait signal is not accepted for instructions that require sequential processing. be.

[0009]

[Operation] During pipeline operation, the processor of the present invention
When a wait signal is received, the flag in the instruction structure corresponding to the wait signal is referred to, and if the instruction accepts the wait signal, the next cycle is executed without waiting for the end of the cycle. Execute. Also, during pipeline operation, a flag in the instruction structure indicating whether or not to accept a wait signal is referred to, and if the instruction does not accept a wait signal, the next cycle is executed after that cycle is completed.

As described above, the processor of the present invention allows wait processing to be performed for any cycle in the pipeline by providing a wait signal and a flag indicating whether or not to accept the wait signal in the instruction structure. This makes it possible to provide a processor capable of faster processing.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of pipeline operation by the processor of the present invention will be described with reference to the drawings.

It is assumed that the processor in this embodiment can execute a maximum of three unprocessed cycles during pipeline operation.

FIG. 1 is an example of a characteristic timing chart of pipeline operation by the processor of the present invention. ADR is an address signal line, WAEN is a wait permission signal line indicating whether or not the cycle accepts a wait.
ADV is the address and WAEN confirmation signal line, DA
TA is a data signal line, DATV is a data confirmation signal line, and WAIT is a cycle wait signal line. Furthermore, A0 to A6 on the ADR are addresses during pipeline operation, and A0 and A3 are accesses that take longer than other cycles and require a wait. D on DATA is data corresponding to the non-pipelined cycle immediately before the A0 cycle. Further, D0 to D6 are data corresponding to the cycle from A0 to A6.

FIG. 2 is an example of a system configuration diagram including the processor of the present invention. (1) CPU is a processor according to the present invention, (2) BUSC is a bus controller that controls the processor bus 6 and I/O bus 7, and I/O access in the pipeline is basically a wait process. shall be necessary. BUSC also determines the cycles of the processor bus and controls the WAIT signal in FIG. (3) MEM is a main memory; (4) MAC is a memory access controller that controls memory access; memory access does not require a wait. (5) I/O is an input/output device connected to the I/O bus 7.

FIG. 3 shows an example of the instruction structure of the processor of the present invention. WF is a flag for determining whether or not the cycle is waitable. In this embodiment, WF is 1.
WF is a waitable cycle and 0 is a waitable cycle. OPC is an operation code, and SRC is a code.
The destination address, DST, is the dest address.

FIG. 4 shows the instruction structure for A0 to A7 in FIG. 1 in accordance with the instruction structure in FIG. 3. Hereinafter, the pipeline operation of the processor according to the present invention will be explained with reference to FIGS. 1 to 4.

The CPU processes the instructions shown in FIG. 4 in a pipeline operation. In order to execute instruction 0 in FIG. 4, the CPU first outputs address A0 on the ADR of the processor bus, and furthermore, as shown in FIG.
Therefore, ADV is output without outputting WAEN. A.D.
Since the address A0 on R is an I/O access as shown in FIG. 4, BUSC immediately accesses the I/O. Since the processor in this embodiment can perform up to three unprocessed cycles during pipeline operation, the CPU executes instructions 1 and 2 in FIG. 4 and writes addresses A1 and A2 on ADR. Further, as shown in FIG. 4, since WF is 1 for instruction 1 and instruction 2, WAEN is output, and ADV is output. At this time, BUSC has not completed the I/O access, and therefore the next new cycle cannot be performed because the CPU is already executing up to three outstanding cycles in pipeline operation.

Next, BUSC completes the I/O access, outputs data D0 on DATA, and then outputs data D0 on DATA.
Output. As a result, the MAC uses addresses A1, A
2, and data D1,
D2 is output one after another, and each output is DATV. Also, after BUSC completed the I/O access, C
The PU executes the next instruction, instruction 3 in FIG.
As shown in Figure 4, instruction 3 outputs address A3 on R, and since WF is 1, it outputs WAEN and AD
Outputs V. BUSC receives I/O address A3 on ADR, performs I/O access, receives WAEN, and outputs WAIT because I/O access requires a wait cycle operation. The CPU executes instruction 3 in Figure 4.
Even after executing the instruction 4, new cycles, instruction 4,
Execute command 5. Also, the WA output from BUSC
Upon receiving IT, the CPU recognizes that instruction 3 is a wait cycle. Further, the MAC outputs data D4 and D5 to addresses A4 and A5 without waiting for data to be output to A3. When the I/O access for instruction 3 is completed, BUSC stops outputting WAIT, and after MAC completes outputting data D5, it outputs data.
At the same time as outputting data D3, it also outputs DATV.

As described above, according to this embodiment, during pipeline operation, subsequent cycles can be completed first without waiting for the completion of a cycle that takes a long processing time, so that the ability of the processor is can be fully utilized. Furthermore, by providing a wait flag in the instruction structure, it is possible to control the change in cycle order.

[0020]

[Effects of the Invention] The processor of the present invention allows the cycle order to be changed for any cycle in the pipeline by providing a wait signal and a flag indicating whether or not to accept a wait in the instruction structure. This makes it possible to provide a processor capable of faster processing.

[Brief explanation of drawings]

FIG. 1 is a characteristic timing chart of pipeline operation by the processor of the present invention;

FIG. 2 is a system block diagram including a processor of the present invention;

[Fig. 3] An explanatory diagram of an example of an instruction structure,

FIG. 4 is an explanatory diagram of a specific instruction structure.

[Explanation of symbols]

ADR: Address signal line, WAEN: Wait permission signal line indicating whether or not the cycle accepts a wait, ADV:
Address and WAEN confirmation signal line, DATA:
DATV: data confirmation signal line, WAIT: cycle wait signal line.

Claims (3)

[Claims] 1. In a processor that performs pipeline processing in which a cycle with a long processing time and a cycle with a short processing time coexist, when the cycle with the long processing time is followed by the cycle with the short processing time, the processing time is 1. A high-speed processor, characterized in that it performs pipeline processing in which the cycle order can be changed, in which the cycle having a short processing time can be completed first without waiting for the completion of the long cycle. 2. According to claim 1, for the long processing time cycle in which the cycle order is to be changed, the processor receives a cycle order change request from another device and performs the cycle in which the cycle order is changed. A high-speed processor that performs reorderable pipeline processing. 3. Pipeline processing according to claim 1 or 2, in which a flag is added to the instruction structure to determine whether or not the cycle order of the cycle can be changed depending on the type of instruction. A high speed processor.