JPH0438245Y2 - - Google Patents
Info
- Publication number
- JPH0438245Y2 JPH0438245Y2 JP12189085U JP12189085U JPH0438245Y2 JP H0438245 Y2 JPH0438245 Y2 JP H0438245Y2 JP 12189085 U JP12189085 U JP 12189085U JP 12189085 U JP12189085 U JP 12189085U JP H0438245 Y2 JPH0438245 Y2 JP H0438245Y2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- value
- memory
- outputs
- switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000005259 measurement Methods 0.000 claims description 12
- 238000001514 detection method Methods 0.000 claims description 7
- 238000006073 displacement reaction Methods 0.000 claims description 2
- 230000003746 surface roughness Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000000700 radioactive tracer Substances 0.000 description 2
- 238000004439 roughness measurement Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
Landscapes
- Measurement Of Length, Angles, Or The Like Using Electric Or Magnetic Means (AREA)
- Length Measuring Devices With Unspecified Measuring Means (AREA)
Description
【考案の詳細な説明】
〈技術分野〉
本考案は表面形状測定装置の測定パラメータに
関するもので、従来、JIS規格ではあらさ測定の
パラメータ表示は中心線平均あらさ(Ra)、最大
高さ(Rmax)、十点平均あらさ(Rz)で規定さ
れていたが、本考案はRzのドイツ規格
(DIN4768)に関する演算表示方法RzDINに関す
るものである。すなわち、トレーサーによつてト
レース方向に沿つて得られた表面のプロフアイル
の隆起面とくぼみ面の面積を一致させる曲線(中
心線)を基準にして演算したあらさ測定のパラメ
ータで測定区間Lnの1/5を単一測定長さeと
し、5つの連続した単一測定長さe1〜e5のそ
れぞれの区間の最高の山頂と最低の谷間の単一あ
らさRz1、Rz2、Rz3、Rz4、Rz5の平均値
RzDIN=1/5(Rz1+Rz2+Rz3+Rz4+Rz5)を出力
する表面形状測定装置の演算表示方法に関するも
のである。[Detailed description of the invention] <Technical field> The present invention relates to the measurement parameters of a surface profile measuring device. Conventionally, according to the JIS standard, parameters for roughness measurement were displayed as center line average roughness (R a ), maximum height (Rmax). ) and ten-point average roughness (Rz), but the present invention relates to the calculation and display method RzDIN regarding the German standard (DIN4768) for Rz . In other words, the roughness measurement parameters calculated based on the curve (center line) that matches the area of the raised surface and the recessed surface of the surface profile obtained along the tracing direction by the tracer are used to calculate the measurement interval L n . Let 1/5 be the single measurement length e, and the single roughness between the highest peak and the lowest valley in each section of five consecutive single measurement lengths e1 to e5 , R z1 , R z2 , R z3 , The present invention relates to an arithmetic display method of a surface shape measuring device that outputs the average value R z DIN=1/ 5 (R z1 +R z2 +R z3 +R z4 +R z5) of R z4 and R z5 .
〈従来技術〉
第3図はこのため従来使用されていた回路であ
つて表面形状により変位する量を検出器から取
り、これを単一測定長e1における最大振幅値を
記憶回路M11に入れ、次にe2の範囲におけるピ
ーク値をM12に入れ順次e3、e4と最大振幅値
をM13、M14に入れ最後にe5の値をM15に入れ
る。すなわち単一測定長e1〜e5のそれぞれの
区間の最高の山頂と最低の谷間の単一あらさRz1
〜Rz5をそれぞれSw11〜Sw15により順次記憶し、
最後に加算器によりRz1+Rz2+Rz3+Rz4+Rz5と
して、次にアツテネータを通して1/5(Rz1+Rz2
+Rz3+Rz4+Rz5)としてRzDINの平均あらさを
計測していた。<Prior art> Figure 3 shows a conventionally used circuit for this purpose, which takes the amount of displacement due to the surface shape from the detector, stores the maximum amplitude value at a single measurement length e1 in the memory circuit M11 , Next, put the peak value in the range of e2 into M12 , sequentially put e3 , e4 and the maximum amplitude value into M13 and M14 , and finally put the value of e5 into M15 . That is, the single roughness R z1 between the highest peak and lowest valley in each section of single measurement length e1 to e5 .
~R z5 are stored sequentially by S w11 ~S w15 , respectively,
Finally, R z1 + R z2 + R z3 + R z4 + R z5 is added using an adder, and then 1/5 (R z1 + R z2
The average roughness of R z DIN was measured as +R z3 +R z4 +R z5 ).
〈解決すべき課題〉
しかし、第3図より明確であるように従来の回
路では最大振幅値検出回路タイミング回路、スイ
ツチ6個、記憶回路5組、加算器、1/5アツテネ
ータにより構成されていたので電子回路が複雑な
上、回路の印刷基板が大きくなり装置が大型にな
つてしまい、しかも高価なものであつた。<Problems to be Solved> However, as is clear from Figure 3, the conventional circuit consisted of a maximum amplitude value detection circuit, a timing circuit, 6 switches, 5 sets of memory circuits, an adder, and a 1/5 attenuator. Therefore, the electronic circuit was complicated and the printed circuit board for the circuit was large, making the device large and expensive.
〈問題を解決する手段〉
そこで本考案では第2図のように最大振幅値検
出回路、1/5アツテネータ、スイツチ4個、タイ
ミング回路、記憶回路2組で構成することにより
部品点数を減らし、回路の印刷基板の小型化も行
なわれ安価なシステム構成とすることが出来た。<Means for solving the problem> Therefore, in the present invention, as shown in Figure 2, the circuit consists of a maximum amplitude value detection circuit, a 1/5 attenuator, four switches, a timing circuit, and two sets of memory circuits to reduce the number of parts and improve the circuit. The size of the printed circuit board has also been reduced, making it possible to create an inexpensive system configuration.
〈実施例〉
第2図において、2つの記憶回路M1、M2は測
定開始前にタイミング回路の信号によりリセツト
され記憶内容を零とする。次に測定が開始される
と、最大振幅値検出回路によりe1の間の最大振
幅値(山と谷の値)を計測し、これを1/5アツテ
ネータ回路に入れ、1/5の信号Rz1/5を作る。
Rz1/5の信号はSw1、Sw2を閉じた時、加算器を
通り記憶回路M1に記憶される。この時Sw2も閉じ
るがM2が零であるのでM1にはe1における最大
振幅値Rz1/5がそのまま記憶される。M1の値は
M2に転入され、転入を開始してSw3を開けM1を
リセツトする。次にe2間における最大振幅値の
1/5の値Rz2/5をe1の計測値が記憶されている
M2の値Rz1/5とを加算器で加算した値Rz1/5
+Rz2/5をM1に記憶し、M2に転入させる。次
に転入を確認し、Sw3を開けM1を転入させる。次
に転入を確認し、Sw2を開けM1りリセツトする。
このようにしてe1〜e5の最大振幅値の1/5の
値が順次加算されM2に入り最後に1/5(Rz1+Rz2
+Rz3+Rz4+Rz5)になつた時Sw4を閉じRzDINの
値として出力させる。なお、スイツチSw1、Sw2、
Sw3、Sw4の開閉及び記憶回路M1、M2のリセツト
のタイミングは第4図に示す。このタイミングは
検出器の相対的移動距離、もしくは測定距離Lの
移動時間からe1、e2、e3……の時間を定め
る方式によるものである。<Embodiment> In FIG. 2, two memory circuits M 1 and M 2 are reset by a signal from a timing circuit to make the stored contents zero before starting measurement. Next, when measurement starts, the maximum amplitude value detection circuit measures the maximum amplitude value (peak and valley value) between e1 , inputs it to the 1/5 attenuator circuit, and outputs the 1/5 signal R z1. Make /5.
When S w1 and S w2 are closed, the signal R z1 /5 passes through the adder and is stored in the memory circuit M 1 . At this time, S w2 is also closed, but since M 2 is zero, the maximum amplitude value R z1 /5 at e1 is stored as is in M 1 . The value of M1 is
Transferred to M2 , start transfer, open S w3 and reset M1 . Next, the measured value of e1 is stored as R z2 /5, which is 1/5 of the maximum amplitude value between e2 .
The value R z1 /5 is obtained by adding the value R z1 /5 of M 2 with the adder.
+R z2 /5 is stored in M 1 and transferred to M 2 . Next, confirm the transfer, open S w3 and transfer M1 . Next, confirm the transfer, open SW2 and reset M1 .
In this way, the value of 1/5 of the maximum amplitude value of e1 to e5 is added sequentially, enters M2 , and finally 1/5 (R z1 + R z2
+R z3 +R z4 +R z5 ), close S w4 and output it as the value of R z DIN. In addition, the switches S w1 , S w2 ,
The opening/closing timing of S w3 and S w4 and the reset timing of memory circuits M 1 and M 2 are shown in FIG. This timing is based on a method of determining the times e1 , e2 , e3 , . . . from the relative movement distance of the detector or the movement time of the measurement distance L.
〈効果〉
本考案においては従来のものと比較して、記憶
回路の数が5個に対し2個、スイツチの数が6個
に対して4個であるのでタイミング回路を含めて
全体の構成が簡単になつて安価に作ることが出来
る。<Effects> In the present invention, compared to the conventional one, the number of memory circuits is 2 compared to 5, and the number of switches is 4 compared to 6, so the overall configuration including the timing circuit is improved. It can be made easily and cheaply.
第1図はあらさ表示規格RzDINの演算内容の
説明図、第2図は本考案の回路の構成を示すブロ
ツク図、第3図は従来の回路のブロツク図、第4
図は本考案の回路におけるタイミングを示す図。
1……測定ワーク、2……トレーサー触針、3
……検出部、4……記憶回路M1、5……記憶回
路M2、6……記憶回路M11、7……記憶回路
M12、8……記憶回路M13、9……記憶回路M14、
10……記憶回路M15、11……最大振幅値検出
回路、12……1/5アツテネータ、13……加算
器、14……タイミング回路。
Fig. 1 is an explanatory diagram of the calculation contents of the roughness display standard Rz DIN, Fig. 2 is a block diagram showing the configuration of the circuit of the present invention, Fig. 3 is a block diagram of the conventional circuit, and Fig. 4
The figure shows the timing in the circuit of the present invention. 1...Measurement workpiece, 2...Tracer stylus, 3
...Detection unit, 4...Memory circuit M1 , 5...Memory circuit M2 , 6...Memory circuit M11 , 7...Memory circuit
M 12 , 8...Memory circuit M 13 , 9... Memory circuit M 14 ,
10...Memory circuit M15 , 11...Maximum amplitude value detection circuit, 12...1/5 attenuator, 13...Adder, 14...Timing circuit.
Claims (1)
を出力する検出器と、 前記検出器からの表面形状信号に基づいて測定
区間Lnの1/5の長さIel,Ie2、……、Ie5毎に、各長
さ区間における最高の山頂と最低の谷間との差を
示す最大振幅値Rz1、Rz2、……、Rz5を検出する
最大振幅値検出回路と、 前記最大振幅値検出回路によつて検出された最
大振幅値Rz1、Rz2、……、Rz5をそれぞれ1/5の値
Rz1/5、Rz2/5、……、Rz5/5にして出力す
る1/5アツテネータと、 2つの入力を加算する加算回路と、 前記加算回路の加算値を一時記憶する第1記憶
回路M1と、 前記第1記憶回路M1の記憶値を記憶する第2
記憶回路M2と、 前記1/5アツテネータで得た1/5の値Rz1/5、
Rz2/5、……、Rz5/5を前記加算回路に出力す
る第1スイツチSw1と、 前記第2記憶回路M2の記憶値を前記加算回路
の他の入力に出力する第2のスイツチSw2と、 前記第1記憶回路M1の記憶値を第2記憶回路
M2に出力する第3スイツチSw3と、 第2記憶回路M2の記憶値をRzDINを示す値と
して出力させる第4スイツチSw4と、 前記第1、第2記憶回路M1、M2及び第1、第
2、第3、第4スイツチSw1〜Sw4を制御する制御
手段であつて、測定開始時に前記第1記憶回路
M1及び第2記憶回路M2の記憶値を零リセツトさ
せ、その後前記1/5アツテネータで1/5の値Rz1/
5、Rz2/5、……、Rz5/5が得られる毎に、そ
の1/5の値が前記加算回路を介して順次螺算され
て前記第2記憶回路M2内に記憶されるように前
記第1、第2及び第3スイツチSw1〜Sw3のオン/
オフを制御し、最終の1/5の値Rz5/5が累算され
ると、前記第4スイツチSw4をオンにする制御手
段と、 を備えたことを特徴とする表面粗さ計の演算回
路。[Claims for Utility Model Registration] A detector that outputs a surface shape signal indicating the amount of displacement of the surface shape of the object to be measured, and a length of 1/5 of the measurement section L n based on the surface shape signal from the detector. For each I el , I e2 , ..., I e5 , the maximum amplitude to detect the maximum amplitude value R z1 , R z2 , ..., R z5 that indicates the difference between the highest peak and the lowest valley in each length section value detection circuit, and the maximum amplitude values R z1 , R z2 , ..., R z5 detected by the maximum amplitude value detection circuit are each 1/5 the value.
A 1/5 attenuator that outputs R z1 /5, R z2 /5, ..., R z5 /5, an adder circuit that adds two inputs, and a first memory that temporarily stores the added value of the adder circuit. a circuit M1 , and a second memory circuit that stores the memory value of the first memory circuit M1 .
The memory circuit M 2 and the 1/5 value R z1 /5 obtained from the 1/5 attenuator,
A first switch S w1 that outputs R z2 /5, ..., R z5 /5 to the addition circuit, and a second switch that outputs the stored value of the second storage circuit M 2 to another input of the addition circuit The switch S w2 and the memory value of the first memory circuit M1 are transferred to a second memory circuit.
a third switch S w3 that outputs to M 2 ; a fourth switch S w4 that outputs the value stored in the second memory circuit M 2 as a value indicating R z DIN; and the first and second memory circuits M 1 , M 2 and the first, second, third, and fourth switches S w1 to S w4 , the control means controls the first storage circuit at the start of measurement.
The stored values of M 1 and the second storage circuit M 2 are reset to zero, and then the 1/5 attenuator is used to set the 1/5 value R z1 /
5. Every time R z2 /5, . . . , R z5 /5 is obtained, the value of 1/5 is sequentially calculated through the adding circuit and stored in the second storage circuit M2 . The first, second and third switches S w1 to S w3 are turned on/off as shown in FIG.
A surface roughness meter comprising: control means for controlling off and turning on the fourth switch S w4 when the final 1/5 value R z5 /5 is accumulated; Arithmetic circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12189085U JPH0438245Y2 (en) | 1985-08-08 | 1985-08-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12189085U JPH0438245Y2 (en) | 1985-08-08 | 1985-08-08 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6230102U JPS6230102U (en) | 1987-02-23 |
| JPH0438245Y2 true JPH0438245Y2 (en) | 1992-09-08 |
Family
ID=31011573
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12189085U Expired JPH0438245Y2 (en) | 1985-08-08 | 1985-08-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0438245Y2 (en) |
-
1985
- 1985-08-08 JP JP12189085U patent/JPH0438245Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6230102U (en) | 1987-02-23 |
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