JPS6230102U - - Google Patents
Info
- Publication number
- JPS6230102U JPS6230102U JP12189085U JP12189085U JPS6230102U JP S6230102 U JPS6230102 U JP S6230102U JP 12189085 U JP12189085 U JP 12189085U JP 12189085 U JP12189085 U JP 12189085U JP S6230102 U JPS6230102 U JP S6230102U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- timing
- memory circuit
- attenuator
- value detection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 238000005259 measurement Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 5
- 239000000700 radioactive tracer Substances 0.000 description 1
Landscapes
- Length Measuring Devices With Unspecified Measuring Means (AREA)
- Measurement Of Length, Angles, Or The Like Using Electric Or Magnetic Means (AREA)
Description
第１図はあらさ表示規格ＲＺＤＩＮの演算内容
の説明図、第２図は本考案の回路の構成を示すブ
ロツク図、第３図は従来の回路のブロツク図、第
４図は本考案の回路におけるタイミングを示す図
。
１：測定ワーク、２：トレーサー触針、３：検
出部、４：記憶回路Ｍ１、５：記憶回路Ｍ２、６
：記憶回路Ｍ１１、７：記憶回路Ｍ１２、８：記
憶回路Ｍ１３、９：記憶回路Ｍ１４、１０：記憶
回路Ｍ１５、１１：ピーク値検出回路、１２：１
／５アツテネータ、１３：加算器、１４：タイミ
ング回路。
Fig. 1 is an explanatory diagram of the calculation contents of the roughness display standard RZDIN, Fig. 2 is a block diagram showing the configuration of the circuit of the present invention, Fig. 3 is a block diagram of a conventional circuit, and Fig. 4 is a diagram of the circuit of the present invention. Diagram showing timing. 1: Measurement workpiece, 2: Tracer stylus, 3: Detection section, 4: Memory circuit M 1 , 5: Memory circuit M 2 , 6
: Memory circuit M 11 , 7: Memory circuit M 12 , 8: Memory circuit M 13 , 9: Memory circuit M 14 , 10: Memory circuit M 15 , 11: Peak value detection circuit, 12: 1
/5 attenuator, 13: adder, 14: timing circuit.
Claims (1)
の１／５の長さのピーク値検出回路、１／５アツ
テネータ、加算回路、記憶回路Ｍ１，Ｍ２及びｌ
ｅ１，ｌｅ２……の間のピーク値を順次追加累算
してＭ１，Ｍ２に入れ、最終のｌｅ５において出
力されるためのスイツチＳｗ１，Ｓｗ２，Ｓｗ３
，Ｓｗ４及びＭ１，Ｍ２のリセツトのタイミング
を取る回路とを有してなる表面粗さ計のＲＺＤＩ
Ｎの演算回路。 Detector outputting surface shape signal, measurement section Lm
A peak value detection circuit with a length of 1/5, a 1/5 attenuator, an addition circuit, and a memory circuit M 1 , M 2 and l
Switches Sw 1 , Sw 2 , Sw 3 are used to sequentially add and accumulate the peak values between e 1 , le 2 .
, Sw 4 and a circuit for timing the reset of M 1 and M 2 .
N arithmetic circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12189085U JPH0438245Y2 (en) | 1985-08-08 | 1985-08-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12189085U JPH0438245Y2 (en) | 1985-08-08 | 1985-08-08 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6230102U true JPS6230102U (en) | 1987-02-23 |
| JPH0438245Y2 JPH0438245Y2 (en) | 1992-09-08 |
Family
ID=31011573
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12189085U Expired JPH0438245Y2 (en) | 1985-08-08 | 1985-08-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0438245Y2 (en) |
-
1985
- 1985-08-08 JP JP12189085U patent/JPH0438245Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0438245Y2 (en) | 1992-09-08 |
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