JPH0438524A - High-speed arithmetic unit - Google Patents

Abstract

PURPOSE:To improve efficiency for an arithmetic processing by providing a clock controller to individually control the clocks of various instructions, and executing the arithmetic processing according to the instruction corresponding to the optimum clock controlled for each instruction. CONSTITUTION:Based on the information of time for executing the instruction, a clock controller 3 controls the clocks having lengths respectively optimum for the various instructions, and this controlled clock is supplied respectively to a sequencer 2 and an instruction register 5. Next, a computing element 6 executes the arithmetic processing according to the instruction corresponding to the clocks respectively optimum for the various instructions. Thus, since the arithmetic processing is executed by the clocks respectively optimum for the various instructions, waiting time between the instructions is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a high-speed arithmetic device in a microcomputer.

(Prior Art) Conventionally, in this type of high-speed arithmetic device, the instruction clock for microprogram control was set to the longest of various instruction clocks to determine the entire clock cycle.

That is, as shown in FIG. 3, the instruction clocks of various instructions Pa, P, , P2, and P3 having different execution times were set to instruction P2, which requires the longest clock.

(Problem to be Solved by the Invention) However, in the microprogram control of the conventional high-speed arithmetic unit described above, the entire instruction clock was set to the instruction P2 having the longest clock, so the execution time was shorter than that of the instruction P2. Instructions Po, P, , p, with
, there is a problem that waiting times Wo, w, , w3 occur, and as a result, the efficiency of arithmetic processing decreases.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, an object of the present invention is to provide a high-speed arithmetic device that eliminates the waiting time between instructions and improves the efficiency of arithmetic processing.

[Structure of the Invention (Means for Solving the Problems) In order to achieve the above-mentioned object, the present invention includes a program memory storing various instructions and recording the execution time of the instructions outputted from the program memory. a clock controller that individually controls the clock of the instruction based on the execution time input to the decoder, and an instruction to which the clock of the controlled instruction and the instruction in the program memory are input. The apparatus includes a register and an arithmetic unit that performs arithmetic processing according to the instructions outputted from the instruction register in synchronization with a clock for each instruction.

(Function) In the present invention, a clock controller that individually controls the clocks of various instructions is provided, and arithmetic processing by the instructions is performed in accordance with the optimum or lock controlled for each instruction, so that the waiting time between instructions is reduced. It disappears.

(Embodiment) An embodiment of the high-speed arithmetic device of the present invention will be described based on FIGS. 1 and 2. Incidentally, FIG. 1 is a block diagram of the high-speed arithmetic device, and FIG. 2 is a time chart showing the operation of the high-speed arithmetic device.

That is, in the drawing, the high-speed arithmetic device includes a program memory 1 in which a program is stored, a sequencer 2 that reads the address of an instruction into the program memory 1, a clock controller 3 connected to this sequencer 2, and a clock controller 3 connected to this sequencer 2. a decoder 4 connected between the controller 3 and the program memory 1;
It consists of an instruction register 5 to which a program memory 1 and a clock controller 3 are connected, and an arithmetic unit 6 connected to the instruction register 5.

Therefore, in a high-speed arithmetic device having such a configuration, first,
Sequencer 2 generates an address, outputs an instruction in program memory 1 specified by the address, and latches this instruction into instruction register 5. Next, in the above instructions,
Information on the execution time is provided and recorded in the decoder 4. Thereafter, the clock controller 3 controls clocks with optimal lengths for various instructions based on the information on the execution time of the instructions, and supplies the controlled clocks to the sequencer 2 and the instruction register 5, respectively. After that,
In the arithmetic unit 6, arithmetic processing according to instructions is performed in accordance with locks that are optimal for various instructions.

In this way, arithmetic processing is performed with locks that are optimal for various instructions, so there is no waiting time between instructions.

[Effects of the Invention] As described above, according to the present invention, arithmetic processing by instructions is performed with optimum locking depending on various instructions, so that unnecessary waiting time between instructions is eliminated. Therefore, calculation processing efficiency and calculation processing speed can be improved. Furthermore, the above-mentioned problems can be solved by easily synchronizing with the sequencer and memory, eliminating the need for the programmer to be aware of the calculation cycle.

[Brief explanation of drawings]

1 and 2 show an embodiment of the device of the present invention, FIG. 1 is a block diagram of the device, FIG. 2 is a time chart explaining the operation of the device, and FIG. 3 is a diagram of the conventional device. It is a time chart explaining the operation. 1...Program memory 2...Sequencer 3...Clock controller 4...Decoder 5...Instruction register 6...Arithmetic unit agent Patent attorney Norihiko Kensuke Patent attorney Takeshi Kondo

Claims (1)

[Claims] A program memory in which various instructions are stored; a decoder that records the execution time of the instructions output from the program memory; and a decoder that records the execution time of the instructions output from the program memory. a clock controller that individually controls the clocks of the instructions; an instruction register to which the clock of the controlled instructions and the instructions in the program memory are input; A high-speed arithmetic device characterized by comprising a arithmetic unit that performs operations in accordance with each clock.