JPH04246727A - Instruction execution method - Google Patents

Abstract

PURPOSE:To set the minimum execution time of an instruction as one operation cycle of an LSI, in an information processor of microprogram control for reading out control storage in two operation cycles. CONSTITUTION:When an instruction is set to an instruction register 11, a microcode is read out of an external control storage 13 through an address generating part 12, and stored in an external microcode register 14. Also, in parallel therewith, read-out to an internal control storage 15 is executed, and the readout microcode is stored in an internal microcode register 16. In the case the instruction to be executed is that which is completed by a single operation cycle of an LSI 10, a selector 18 sends the contents of the internal microcode register 16 to a decoder 19, and by this microcode, an arithmetic control circuit 20 is controlled.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to an instruction execution method in a microprogram-controlled information processing device, and in particular,
The present invention relates to an instruction execution method suitable for use in a microprogram-controlled information processing device configured using an LSI.

0002

2. Description of the Related Art In recent microprogram-controlled information processing devices, as LSIs become more highly integrated and faster, the access speed of control memory memory elements that store microcodes has become slower than the operating speed of the LSIs. It's coming. For this reason, this type of information processing apparatus cannot finish reading the next microcode before the execution of one microcode ends, resulting in wasted time during the execution of the microprogram.

[0003] As a conventional technique for solving the above-mentioned problems, for example, a technique described in Japanese Patent Application Laid-Open No. 61-223948 is known. This conventional technology is
The unit of reading from the control memory is two consecutive micro orders, thereby eliminating wasted time during execution of the micro program.

0004

[Problems to be Solved by the Invention] In the prior art, even when executing an instruction with the shortest processing time, the instruction is
Since it is composed of one micro-order, it has the problem that the minimum instruction execution time is twice as long as the LSI operation cycle.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art, to make it possible to reduce the minimum execution time of an instruction to one operation cycle of an LSI in a microprogram-controlled information processing device, and to improve the information processing device. The object of the present invention is to provide an instruction execution method that can improve overall processing performance.

[0006]

[Means for Solving the Problems] According to the present invention, the above object is to provide an LSI processor having an instruction execution control section and a microprogram control section, in which the memory is read out only at the start of instruction execution, separately from an external control memory. an internal control memory is provided inside the LSI, the internal control memory is readable in an operating cycle of the LSI, and the read data of the internal control memory is read only at the start of execution of an instruction that is completed in one operating cycle of the LSI. This is achieved by using it as microcode.

[0007]

[Operation] By making the internal control memory readable in the operating cycle of the LSI, and using the read data of the internal control memory as microcode only at the start of execution of an instruction that is completed in one operating cycle of the LSI, It becomes possible to execute instructions with a short processing time in one operation cycle of the LSI, and it is possible to improve the processing capacity of the entire device.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the instruction execution method according to the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing a simplified configuration of an information processing apparatus according to an embodiment of the present invention in order to explain the operating principle of the present invention. First, the operating principle of the present invention will be explained with reference to FIG. do. In FIG. 1, 10 is an LSI, 11
12 is an instruction register, 12 is an address generator, 13 is an external control memory, 14 is an external microcode register, and 15 is an LS.
16 is an internal microcode register, 18 is a selector, 19 is a decoder, and 20 is an arithmetic control circuit.

The microprogram-controlled information processing device shown in FIG. 1 includes an LSI 10 constituting a microprogram-controlled information processing section, and a control memory 13 provided outside the LSI 10. The external control memory 13 stores microcodes similar to those in the prior art, and the internal control memory 15 stores:
According to the present invention, microcode of instructions that are completed in one operation cycle of the LSI 10 is stored.

Furthermore, although the external control memory 13 has a large capacity, the readout time thereof is twice as long as that of the internal control memory 15. On the other hand, the internal control memory 15 has a very small capacity and cannot control all operations of the microprocessor by itself, but it can be read in one operation cycle of the LSI 10.

In the information processing device configured as described above, when an instruction is set in the instruction register 11, its contents are supplied to the address generation section 12 and stored in the external control memory 1.
3 is created, and the microcode is read from the external control memory 13 using this address and stored in the external microcode register 14.

Furthermore, at the start of execution of an instruction, reading from the internal control memory 15 is performed in parallel with reading from the external control memory 13. The address for the internal control memory 15 at this time is created based on the contents of the instruction register 11. The read microcode is then stored in the internal microcode register 16.

When the instruction to be executed is one that can be completed in one operation cycle of the LSI 10, the selector 18
The internal microcode register 16 is controlled to be selected, the contents of the internal microcode register 16 are sent to the decoder 19, and the arithmetic control circuit 20 is controlled by this microcode.

If the instruction to be executed is not completed in one operation cycle of the LSI 10, the selector 18 is controlled to select the external microcode register 14, and the contents of the external microcode register 14 are transferred to the microdecoder. 19, and the arithmetic control circuit 20 is controlled by this microcode.

As described above, the present invention stores the microcode of an instruction that is completed in one operation cycle of the LSI 10 in the internal control memory, and when the instruction is stored in the instruction register, the microcode of the instruction is stored in the external control memory. By reading microcodes from both the and internal control memory and using one of the microcodes to control the arithmetic control circuit, instructions that can be processed in a short time can be processed in one operation cycle of the LSI 10. This allows the program to be terminated with .

Next, details of one embodiment of the instruction execution method of the present invention will be explained.

FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 3 is a timing chart explaining the operation. In FIG. 2, 32 is an instruction code section, 38 and 40 are delay registers, 39 is a one-cycle operation bit, and other symbols are the same as in FIG. 1.

An embodiment of the present invention, as shown in FIG.
A microprogram control unit including an address generation circuit 12, an external control memory 13, an external microcode register 14, an instruction register 11, an internal control memory 15, an internal microcode register 16, a 1-cycle operation bit 39,
an instruction execution control unit using delay registers 38 and 40;
It is configured to include a selector 18, a decoder 19, and an arithmetic unit 20 including an arithmetic selector circuit 20.

Internal control memory 15 provided according to the invention
As mentioned above, is read out simultaneously with the external control memory 13, but after being set in the internal microcode register 16, the readout output is transmitted from the readout output of the external control memory 13 via the delay register 38 for one operation. It is input to the selector 18 after a cycle delay. Also, the instruction code 32 in the instruction register 11 has a one-cycle operation bit 39.
After being converted into a 1-bit signal for controlling the selector 18, the signal is delayed by one operation cycle via the delay register 40 and then provided to the selector 18.

Next, referring to FIG. 3, the operation of an embodiment of the present invention configured as described above will be described. As shown in FIG. The operation when performed in order will be explained.

The execution cycles of the instruction B1 that precedes the instruction A are ① and ②, and in these cycles, the instruction B1 is executed by the arithmetic unit.

In cycle (2), instruction A is set in the instruction register 11, and its instruction code 32 is sent to the address generation circuit 12. As a result, the external control memory 13 of the LSI 10 spends cycles (2) and (2) to read the microcode. The external control memory 13
The read data is set in the external microcode register 14 in cycle (2).

In parallel with this operation, the internal control memory 15 of the LSI 10 is read using the instruction code 32 of the instruction register 11 as an address. Since reading from the internal control memory 15 is faster than reading from the external control memory 13, it is completed in cycle (2), and the read data is set in the internal microcode register 16 in cycle (2). Thereafter, the contents of the internal microcode register 16 are set to the delay register 38 in cycle 2. This allows reading of the internal control memory 15 and external control memory 13.
The reading of the data is synchronized with the reading of the data.

Furthermore, in parallel with the above-mentioned reading of the internal control memory 15, the one-cycle operation bit 39 determines the contents of the instruction code 32, and determines whether the instruction is an instruction that is completed in one operation cycle of the LSI, in this example. , A instruction, "1" is output in cycle (2), and the delay register 40 outputs "1" in cycle (2).

Therefore, the selector 18 selects the delay register 38 which is the contents of the internal microcode register 36.
The content is sent to the decoder 42 to instruct the arithmetic control circuit 20 to operate. The arithmetic control circuit 20 executes the instruction A by
Using only the data in the internal control memory 15, the cycle ■
The process ends in one cycle.

On the other hand, in parallel with the above-mentioned operation, the cycle
Then, instruction B2 following instruction A is set in the instruction register 11. As in the case of instruction A, external control memory 1
3 and internal control memory 15 are performed in parallel, and in cycle (2), read data from these is set in external microcode register 14 and delay register 38. On the other hand, since the instruction code 32 is instruction B2, the one-cycle operation bit 39 is set as instruction B2.
Since this is not an instruction that can be processed in one operation cycle, "0" is output in cycle (2), and the delay register 40 of the one-cycle operation bit 39 is set to "0" in cycle (2). Therefore, the selector 18 sends the contents set in the external microcode register 14 to the decoder 19.

Here, for reading the external control memory 34, two steps are required.
Although it takes several cycles, the contents of the external microcode register 14 are stored in the arithmetic unit in one cycle, because the microcode for two cycles is read out in one readout.
, cycle ■ will be controlled. In this way, execution of the instruction B2 is completed without using the data in the internal control memory 15.

As described above, according to the embodiment of the present invention,
Since the internal control memory 15 is read each time at the start of execution of each instruction without distinguishing between one-cycle instructions and instructions of two or more cycles, the internal control memory read control circuit can be simplified.

Further, according to the embodiment of the present invention, since a RAM is used for the internal control memory 15, if a defect in the internal control memory data is discovered while the apparatus according to the embodiment of the present invention is in operation. It is also easy to modify the data.

In the above-described embodiment of the present invention, the internal control memory 15 is read every time when the execution of each instruction starts. The internal control memory 15 may be read only in the internal control memory 15, or the internal control memory 15 may have a function corresponding to the one-cycle operation bit 39.

[0032]

[Effects of the Invention] As explained above, according to the present invention, L
By providing a small capacity internal control memory inside the SI,
It becomes possible to set the minimum execution time of an instruction to one operation cycle of the LSI regardless of the read time of the external control memory, and it is possible to improve the processing capacity of the entire device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a simplified configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 3 is a timing chart explaining the operation.

[Explanation of symbols]

10 LSI 11 Instruction register 13 External control memory 14 External microcode register 15 Internal control memory 16 Internal microcode register 18 Selector 19 Decoder 20 Arithmetic control circuit 32 Instruction code section 38, 40 delay register 39 1 cycle operation bit

Claims (2)

[Claims] 1. An information processing device comprising an instruction execution control section and a microprogram control section, wherein the instruction execution control section and the microprogram control section are housed in the same integrated circuit. It is characterized by comprising an external control memory outside the integrated circuit that is read every time the microcode is executed, and an internal control memory storing a microcode that can be executed in one operation cycle of the integrated circuit inside the integrated circuit. An instruction execution method that 2. The internal control memory is read only at the start of instruction execution, and the instruction whose execution is completed in one operation cycle of the integrated circuit is controlled using only read data from the internal control memory, An instruction execution method characterized in that an instruction requiring twice or more the operating cycle of the integrated circuit is controlled using only read data from the external control memory.