JPH0440140A - Advanced start priority circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] Regarding a circuit that gives first priority to transmission data, the circuit scale can be reduced and the delay time from inputting a specific code to input data to outputting it can be reduced. The purpose of the present invention is to provide a first priority circuit which prevents an increase in data storage means, and which maintains the output state of a specific code when an input of the specific code is given, and also maintains the output state of the specific code of any data holding means other than itself. N reset by output state
(N is a natural number of 2 or more) data holding means are provided, and among the input data of the N data holding means, input data that becomes a specific code first is held and outputted, and later becomes the specific code. construct by ignoring all input data.

[Industrial application field]

The present invention relates to a circuit that prioritizes a plurality of transmission data, and in particular, prioritizes input data that first becomes a code "1" among a plurality of input data, and inputs that become a code "1" later. It concerns a first-first priority circuit for ignoring data.

The first priority circuit is used in a data transmission device or the like when it is necessary to give priority to input data and perform data manipulation.

It is desired that such a first-movement priority circuit be realized with as small a circuit scale as possible.

[Conventional technology]

FIG. 5 shows an example of the configuration of a conventional first-movement priority circuit for two katators D, . . . , D, .

As shown in the figure, it includes a flip-flop 11.12, Nant gates 21, 22, and an inverter 31.32, and input data DKI is connected to one input terminal of the Nant gate 21, and the output of the Nant gate 22 is connected to the other input terminal. are connected to perform a NAND operation, connect the input data ntz to one input terminal of the Nante gate 22, connect the output of the Nante gate 21 to the other input terminal to perform a NAND operation, and connect the respective outputs to the inverter 21. .22, the sign is inverted, and then input to the data input terminals of flip-flops 31 and 32, respectively.

Further, a clock signal CK is applied to the clock input terminal CK of the flip-flops 31 and 32, and output data D is output from each output terminal Q. I+DO! It has a configuration that outputs .

In the first priority circuit shown in FIG.
When , if the input at the other input terminal is also a sign “1”, the output of the Nant gate 21 will be a sign “0”, so
The output of the inverter 31 becomes the code "1", and the flip-flop 11 performs synchronization with the clock signal CK to generate output data DOI with the code "1".

In this state, the input data D+ of the other Nantes gate 22
Even if z is input with the code “1”, the input
Since the output of the flip-flop 12 does not have the code "1", the output data I)ox of the flip-flop 12 does not have the code "1".

That is, the input data D1 with the code "1" added later to the Nant gate 21 is ignored, and the first priority operation is performed.

FIG. 6 shows an operation timing chart of the conventional first priority circuit, and shows the input DI+ of the Nant gate 21.
As a result, the output of the inverter 31 becomes "1" as shown in (A), and as a result, the output of the flip-flop 11 also becomes "1". l sign °
It is shown that the input I)+z of the Nant gate 22 does not produce the sign "1" at the output Dog. At this time, the output (A) of the inverter 31 and the output of the flip-flop 11. The code “1” in I
The occurrence of ``is gradually delayed due to operational delays of circuit elements, and it has been shown that the delay in Nandt gates is particularly large.

[Problem to be solved by the invention]

The conventional first-first priority circuit shown in FIG. 5 requires the same number of Nant gates, inverters, and flip-flops as the number of inputs, and therefore has the problem of increased circuit scale, especially when the number of inputs increases. be.

Also, if the circuit format shown in Figure 5 has a large number of inputs, a multi-input NAND gate is used on the input side, but in order to realize such a multi-input NAND gate, multiple stages of gates may be stacked. However, this increases the delay time, and there is a problem that it takes time from when the code "1" is input to the input data until it is output.

FIGS. 7(a) and 7(b) explain the gate expansion of a multi-input NAND gate. When the 8-man powered NAND gate 41 shown in FIG. 7(a) is expanded, for example, a two-stage Gates 51-56 and Nantes Gate 57
A three-stage gate configuration is required.

When the number of gate stages is large as described above, the delay time becomes significantly large.

The present invention aims to solve the problems of the prior art as described above, and is capable of reducing the circuit scale in the first priority circuit, and also enables the reduction of the circuit scale from the input of the code "1" to the input data to the output. The purpose of the present invention is to provide a first-movement priority circuit that prevents an increase in delay time.

[Means to solve the problem]

The present invention has N(N
is a natural number of 2 or more) data holding means 11.12, -
・Equipped with +1N. These N data holding means 1. ．． 1! , -, 1N holds the output state of the specific code when the input of the specific code is given, and is reset by the output state of the specific code of any data holding means other than itself, so that N Data holding means I1.12.

, 1N input data that first becomes a specific code is held and output, and all input data that becomes the specific code later is ignored.

[Effect]

The N data holding means 111 1 z, -, I N are
When given an input of a specific code, it generates an output of a specific code and maintains the output state. Also, N data holding means 1. ．． 12, −・+ 1N is the logical sum means 2,
, 2, . . . -'2N, it is reset by the output state of a specific code of any data holding means other than itself. As a result, N data holding means 11, 12, ..., 1
It functions as a first priority circuit that holds and outputs the input data that first becomes a specific code among the N input data, and ignores all input data that becomes a specific code later, but the circuit configuration in this case is In addition to being simple, since there are no gates or the like on the input/output lines of the data holding means, the time from input data being applied until output data is generated is short.

〔Example〕

FIG. 2 shows an embodiment of the present invention, and shows a configuration including flip-flops 101.10□ and gates 201.201.

As shown in the figure, input data DI+ is connected to the data input terminal of the flip-flop 101, and output data Dot is taken out from the output terminal Q of the flip-flop 101.
Flip flop 10! The input data I)+z is connected to the data input terminal of the flip-flop 10z, and the output data I)oz is taken out from the output terminal Q of the flip-flop 10z.

In addition, the gate 20 performs the logical product of the signal at the inverting output terminal XQ of the flip-flop 10t and the reset signal XRESET.
．． Find it, flip-flop 10, glue set terminal
RESET, and the signal of the inverting output terminal XQ of the flip-flop 101 and the reset signal X RESET
and the gate 2oz, and the flip-flop 10. Connect to the reset terminal XRESET of

Furthermore, flip-flops 101, 10 . A clock signal CK is connected to the clock terminal CK of.

FIG. 3 is a diagram showing an operation timing chart of the embodiment of FIG. 2.

Initially, when the code "0" is given as the reset signal XRESET, as shown in (A) and (B), the game
Since the outputs of each of 20+ and 20g have the sign "0", the flip-flop 10. ．． 10□ is initialized,
The output of each output terminal Q has a code of "0", and the output of the inverted output terminal XQ has a code of "1".

Next, when the code "1" is applied as the reset signal XRESET, this circuit enters the operating state.

For example, when the input data D I 1 becomes the code "1",
At the rising edge of clock signal CK, flip-flop 1
“1” is output to the output terminal Q of 01, and the output data D
, is held as a code "1", and a code "0" is output to the inverting output terminal XQ.

Flip flop 10. The code “0” is applied to the inverted output terminal XQ of
'' is output, the output of the gate 208 becomes the sign "0", and therefore the flip-flop 10! enters the reset state.

Therefore, the input data DIz of the flip-flop Log
Even if the code “1” is given to the flip-flop 10!
cannot be set. Therefore, the input data Dl!
The code "1" in is ignored, and priority is given to the input data D11 to which the code "1" is given first.

In this case, in the flip-flops iot, ioz,
Clock signal C changes input data DIl+DI2
By reading with K, the output data D is immediately read.
. l+Do! As in the conventional technology,
This solves the problem that it takes a long time for the code "1" to be output after it is input to the input data.

FIG. 4 shows another embodiment of the present invention, in which N
input data D++, DI! ! +-・-, D1N
The corresponding configuration is shown.

Flip-flop l Ol+ 10! ,・・・・・・,
10 N is input data DIl+I)+z,'
-1I)+s are respectively connected to the data input terminals,
Output data Dot, Do from each output terminal Q
z+-, DON is taken out.

The reset terminals XRESET of each flip-flop 10+, 10g, . . . , 1ON have gates 20+,
20□, -・-92ON outputs are connected, each game) 2
0. ．． The inverted outputs XQ of each flip-flop other than the corresponding flip-flops 101.10t, -', 10N are connected to the inputs of 20□, -., 20H.

Also, each flip-flop 10. , 10□, and -2108 are commonly connected to the clock signal CK.

In the embodiment shown in FIG. 4, as in the embodiment shown in FIG. 2, the input data D, , D, .

−・−, the code “1” is given to either D1N,
When the code "1" is output to the output terminal Q of the corresponding flip-flop, the reset terminals XRESET of all other flip-flops become the code "0", so other input data later becomes the code "1". However, since the flip-flop is in the reset state, its input data is ignored, and the same first-first-first-first-first-served operation as in the embodiment of FIG. 2 is performed.

In the first priority circuit shown in FIGS. 2 and 4, the fifth
Compared to the conventional first-first priority circuit shown in the figure, one inverter can be saved per person, resulting in a smaller circuit scale. Furthermore, since there are no gates or the like on the input/output lines of the flip-flop, an increase in the delay time from when input data is added to when output data appears is prevented.

In addition, in the present invention, the input of the specific code given priority to the first person is the code “
The code is not limited to "1" and may be the code "0".

〔Effect of the invention〕

As explained above, in the first-start priority circuit of the present invention, the circuit scale is reduced compared to the conventional circuit. Furthermore, the time from when input data is added to when output data is generated is short, so according to the present invention, it is possible to simplify the first priority circuit and improve its characteristics.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the basic configuration of the present invention, FIG. 2 is a diagram showing an embodiment of the present invention, FIG. 3 is a diagram showing an operation timing chart of the embodiment of FIG. 2, and FIG. 5 is a diagram showing a conventional first priority circuit, FIG. 6 is a diagram showing an operation timing chart of the conventional first priority circuit, and FIGS. ) is a diagram explaining gate expansion of a multi-input NAND gate. 1 r, 1 g, '----' I N is a flip-flop, 2 I, 2 g. -.-2N is an OR circuit.

Claims (1)

[Claims] N that holds the output state of the specific code when an input of the specific code is given, and is reset by the output state of the specific code of any data holding means other than itself.
(N is a natural number of 2 or more) data holding means (1_1,
1_2, ..., 1_N), and holds the input data that becomes a specific code first among the input data of the N data holding means (1_1, 1_2, ..., 1_N). A first priority circuit characterized in that it outputs and ignores all input data that later becomes the specific code.