JPH0440271Y2 - - Google Patents
Info
- Publication number
- JPH0440271Y2 JPH0440271Y2 JP1982150194U JP15019482U JPH0440271Y2 JP H0440271 Y2 JPH0440271 Y2 JP H0440271Y2 JP 1982150194 U JP1982150194 U JP 1982150194U JP 15019482 U JP15019482 U JP 15019482U JP H0440271 Y2 JPH0440271 Y2 JP H0440271Y2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- resistor
- semiconductor substrate
- insulating layer
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
Landscapes
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
Description
【考案の詳細な説明】
この考案はトランジスタ装置に係り、特に酸化
膜上に形成された薄膜抵抗等の半導体素子に設置
する電極構造に関する。[Detailed Description of the Invention] This invention relates to a transistor device, and particularly to an electrode structure installed in a semiconductor element such as a thin film resistor formed on an oxide film.
第１図は従来の半導体装置の一部を示し、シリ
コン等の半導体基板２の表面に設置した酸化膜４
の表面には、薄膜抵抗６が形成されている。この
薄膜抵抗６の端部には、図示していない他の半導
体素子に電気的に接続する配線導体８が設置され
るとともに、薄膜抵抗６の表面部にはアルミニウ
ム、金等の金属材料を蒸着して電極１０が形成さ
れている。 FIG. 1 shows a part of a conventional semiconductor device, in which an oxide film 4 is placed on the surface of a semiconductor substrate 2 made of silicon or the like.
A thin film resistor 6 is formed on the surface. A wiring conductor 8 that electrically connects to another semiconductor element (not shown) is installed at the end of the thin film resistor 6, and a metal material such as aluminum or gold is deposited on the surface of the thin film resistor 6. Thus, the electrode 10 is formed.
このように薄膜抵抗６の表面に形成された電極
１０にリードワイヤを溶接した場合、電極１０と
薄膜抵抗６との接合強度が一般に低いために、電
極１０が薄膜抵抗６から剥離して電気的接続状態
が不十分となり、歩留りが悪化する等の欠点があ
つた。 When a lead wire is welded to the electrode 10 formed on the surface of the thin film resistor 6 in this way, since the bonding strength between the electrode 10 and the thin film resistor 6 is generally low, the electrode 10 may peel off from the thin film resistor 6 and the electrical There were drawbacks such as poor connection and poor yield.
そこで、この考案は、電極の固着強度を強化す
ることにより、電極剥離等の防止を図つたトラン
ジスタ装置を提供することを目的とする。 Therefore, an object of this invention is to provide a transistor device that prevents electrode peeling by increasing the adhesion strength of the electrodes.
即ち、この考案のトランジスタ装置は、平面形
状が矩形を成す半導体基板１２と、この半導体基
板で唯一のコレクタを構成し、前記半導体基板の
表面層にベース２０を形成し、このベースの内部
にエミツタ２２を形成して成る単一のトランジス
タ１４と、前記半導体基板の表面を覆う絶縁層
（酸化膜２４）と、この絶縁層上に形成された第
１及び第２の抵抗（薄膜抵抗１６，１８）と、前
記第１及び第２の抵抗の一端に接続されていると
ともに、前記絶縁層に形成された開口を通して前
記ベースに接続された第１の電極２６と、前記第
２の抵抗の他端に接続されるとともに、前記絶縁
層に形成されている開口を通して前記エミツタに
接続された第２の電極２８と、前記第１の抵抗の
他端に接続される第３の電極３２とを備えるとと
もに、前記半導体基板に対して一つの角部側の矩
形領域に前記ベースを配置し、前記角部側と対角
線上の角部側に前記第３の電極を配置し、前記ベ
ースと前記半導体基板の一辺部との間における領
域に前記第１の抵抗、前記ベースと前記半導体基
板の他辺部との間における領域に前記第２の抵抗
を配置したトランジスタ装置であつて、前記第１
の電極は前記第１及び第２の抵抗の電極形成部と
その周囲部の前記絶縁層、第２の電極は前記第２
の抵抗の電極形成部とその周囲部の前記絶縁層、
前記第３の電極は前記第１の抵抗の電極形成部と
その周囲部の絶縁層に跨がつて設置したことを特
徴とする。 That is, the transistor device of this invention includes a semiconductor substrate 12 having a rectangular planar shape, this semiconductor substrate forming the only collector, a base 20 formed on the surface layer of the semiconductor substrate, and an emitter inside the base. 22, an insulating layer (oxide film 24) covering the surface of the semiconductor substrate, and first and second resistors (thin film resistors 16, 18) formed on this insulating layer. ), a first electrode 26 connected to one ends of the first and second resistors and connected to the base through an opening formed in the insulating layer, and the other end of the second resistor. and a second electrode 28 connected to the emitter through an opening formed in the insulating layer, and a third electrode 32 connected to the other end of the first resistor. , the base is disposed in a rectangular region on one corner side with respect to the semiconductor substrate, the third electrode is disposed on a corner diagonal side with respect to the corner side, and the base and the semiconductor substrate are The first resistor is arranged in a region between the base and the other side of the semiconductor substrate, and the second resistor is arranged in a region between the base and the other side of the semiconductor substrate, the transistor device comprising:
The electrode includes the electrode forming portions of the first and second resistors and the insulating layer surrounding the electrodes, and the second electrode includes the electrode forming portions of the first and second resistors and the insulating layer around the electrode forming portions of the first and second resistors.
the electrode forming portion of the resistor and the insulating layer around the resistor;
The third electrode is characterized in that it is installed so as to straddle the electrode formation portion of the first resistor and the insulating layer around the electrode formation portion.
以下、この考案を図面に示した実施例を参照し
て詳細に説明する。 Hereinafter, this invention will be described in detail with reference to embodiments shown in the drawings.
第２図及び第３図はこの考案の実施例を示し、
第２図はその平面部の構成、第３図は第２図の
−線に沿う断面を示している。 Figures 2 and 3 show an embodiment of this invention,
FIG. 2 shows the structure of the planar part, and FIG. 3 shows a cross section taken along the line - in FIG.
図において、シリコン等で形成された平面形状
が矩形を成す半導体基板１２には、単一のトラン
ジスタ１４とともに第１及び第２の抵抗として薄
膜抵抗１６，１８が設置されている。即ち、半導
体基板１２の表面層には、半導体基板１２で唯一
のコレクタが形成されているとともに、半導体基
板１２の表面層には、半導体基板１２の一つの角
隅部側の領域に矩形状を成すベース２０が形成さ
れ、そのベースの内部にエミツタ２２が形成され
ている。 In the figure, a single transistor 14 and thin film resistors 16 and 18 as first and second resistors are installed on a semiconductor substrate 12 made of silicon or the like and having a rectangular planar shape. That is, the only collector in the semiconductor substrate 12 is formed in the surface layer of the semiconductor substrate 12, and a rectangular shape is formed in the surface layer of the semiconductor substrate 12 in a region on the side of one corner of the semiconductor substrate 12. A base 20 is formed, and an emitter 22 is formed inside the base.
また、半導体基板１２の表面には絶縁層として
SiO2等の酸化膜２４が形成され、この酸化膜２
４の表面には、薄膜抵抗１６，１８が真空蒸着等
で形成された帯状を成すポリシリコン層で構成さ
れている。即ち、薄膜抵抗１６，１８は、酸化膜
２４の上面にトランジスタ１４のベース２０及び
エミツタ２２の上面を避けて設置されており、薄
膜抵抗１６はベース２０と半導体基板１２の一辺
部との間の領域に、また、薄膜抵抗１８はベース
２０と半導体基板１２の他辺部との間の領域にそ
れぞれ形成されている。 Further, an insulating layer is formed on the surface of the semiconductor substrate 12.
An oxide film 24 such as SiO 2 is formed, and this oxide film 2
On the surface of 4, thin film resistors 16 and 18 are formed of a band-shaped polysilicon layer formed by vacuum evaporation or the like. That is, the thin film resistors 16 and 18 are installed on the top surface of the oxide film 24 while avoiding the top surface of the base 20 and emitter 22 of the transistor 14, and the thin film resistor 16 is placed between the base 20 and one side of the semiconductor substrate 12. The thin film resistor 18 is formed in the region between the base 20 and the other side of the semiconductor substrate 12.
そして、トランジスタ１４のベース２０又はエ
ミツタ２２を覆う酸化膜２４の表面部には、コン
タクトウインドを形成し、アルミニウム又は金等
を蒸着して電極２６，２８が個別に形成され、ベ
ース２０の電極２６は、薄膜抵抗１６，１８の端
部に延長されて電気的に接続されている。また、
エミツタ２２の電極２８は、薄膜抵抗１８の端部
に延長されて電気的に接続されている。 A contact window is formed on the surface of the oxide film 24 covering the base 20 or the emitter 22 of the transistor 14, and electrodes 26 and 28 are formed individually by vapor depositing aluminum or gold. are extended and electrically connected to the ends of the thin film resistors 16 and 18. Also,
The electrode 28 of the emitter 22 is extended and electrically connected to the end of the thin film resistor 18.
薄膜抵抗１６の一方の端部には電極形成部３０
が設定され、この電極形成部３０は薄膜抵抗１６
の本体部より幅広の矩形形状に形成されている。
この電極形成部３０には、その上面を覆うととも
に電極形成部３０に隣接する酸化膜２４の一部を
覆つて第３の電極３２が形成されている。この電
極３２は、電極２６，２８と同時に形成される。 An electrode forming portion 30 is provided at one end of the thin film resistor 16.
is set, and this electrode forming portion 30 has a thin film resistor 16
It is formed into a rectangular shape that is wider than the main body.
A third electrode 32 is formed on the electrode forming portion 30 so as to cover the upper surface thereof and a part of the oxide film 24 adjacent to the electrode forming portion 30 . This electrode 32 is formed at the same time as electrodes 26 and 28.
このように電極形成部３０を覆い且つ隣接する
酸化膜２４の一部を包含するように電極３２を構
成すれば、電極３２は酸化膜２４の表面に接合さ
れ、その接合力は薄膜抵抗１６との間より強固に
行われるので、薄膜抵抗１６との電気的接続は良
好になるとともに、従来生じていた薄膜抵抗から
の剥離等の不都合を確実に防止することができ
る。 If the electrode 32 is configured to cover the electrode forming portion 30 and include a part of the adjacent oxide film 24 in this way, the electrode 32 will be bonded to the surface of the oxide film 24, and the bonding force will be the same as that of the thin film resistor 16. Since the connection is made more firmly during the process, the electrical connection with the thin film resistor 16 is improved, and inconveniences such as separation from the thin film resistor, which conventionally occur, can be reliably prevented.
次に、第４図及び第５図は、この考案のトラン
ジスタ装置の他の実施例を示す。 Next, FIGS. 4 and 5 show other embodiments of the transistor device of this invention.
前記実施例では、電極３２の各辺が薄膜抵抗１
６の端部に設定された電極形成部３０の矩形形状
に対応してほぼ２倍に設定され、その一辺部側を
一致させているが、第４図及び第５図に示すよう
に、電極３２の中央部に薄膜抵抗１６の電極形成
部３０を設定してもよい。電極形成部３０の中央
部に開孔３４を形成して酸化膜２４を露出させ、
その酸化膜２４、薄膜抵抗１６の電極形成部３０
及びその周囲の酸化膜２４に電極３２を形成すれ
ば、電極３２と薄膜抵抗１６との接合はより強固
なものとなる。 In the above embodiment, each side of the electrode 32 has a thin film resistor 1
The size of the electrode forming portion 30 is approximately twice that of the rectangular shape corresponding to the rectangular shape of the electrode forming portion 30 set at the end of the electrode. The electrode forming portion 30 of the thin film resistor 16 may be set at the center of the thin film resistor 16 . An opening 34 is formed in the center of the electrode forming part 30 to expose the oxide film 24,
The oxide film 24 and the electrode forming portion 30 of the thin film resistor 16
If the electrode 32 is formed on the oxide film 24 around the electrode 32, the bond between the electrode 32 and the thin film resistor 16 becomes stronger.
以上説明したように、この考案によれば、第１
の電極は第１及び第２の抵抗の電極形成部とその
周囲部の絶縁層、第２の電極は第２の抵抗の電極
形成部とその周囲部の絶縁層、第３の電極は第１
の抵抗の電極形成部とその周囲部の絶縁層に跨が
つて設置したので、電極と抵抗の電気的接続が良
好になるとともに、電極の固着強度を強化するこ
とができ、従来、リードボンデイング時に生じて
いた電極剥離等の不都合を未然に防止できる。 As explained above, according to this invention, the first
The electrodes are the electrode formation portions of the first and second resistors and the insulating layer around them, the second electrode is the electrode formation portion of the second resistor and the insulation layer around the surroundings, and the third electrode is the insulation layer around the electrode formation portions of the first and second resistors.
Since it is installed across the electrode formation part of the resistor and the insulating layer around it, it not only improves the electrical connection between the electrode and the resistor, but also strengthens the adhesion strength of the electrode. Inconveniences such as electrode peeling can be prevented.
第１図は従来の半導体装置の電極構造を示す断
面図、第２図はこの考案のトランジスタ装置の実
施例を示す平面図、第３図は第２図に示したトラ
ンジスタ装置の−線断面図、第４図はこの考
案のトランジスタ装置の他の実施例を示す平面
図、第５図は第４図に示したトランジスタ装置の
−線断面図である。
１２……半導体基板、１４……トランジスタ、
１６……薄膜抵抗（第１の抵抗）、１８……薄膜
抵抗（第２の抵抗）、２０……ベース、２２……
エミツタ、２４……酸化膜（絶縁層）、２６……
第１の電極、２８……第２の電極、３２……第３
の電極。
FIG. 1 is a cross-sectional view showing the electrode structure of a conventional semiconductor device, FIG. 2 is a plan view showing an embodiment of the transistor device of this invention, and FIG. 3 is a cross-sectional view taken along the - line of the transistor device shown in FIG. 4 is a plan view showing another embodiment of the transistor device of this invention, and FIG. 5 is a sectional view taken along the line -- of the transistor device shown in FIG. 12...Semiconductor substrate, 14...Transistor,
16... thin film resistor (first resistor), 18... thin film resistor (second resistor), 20... base, 22...
Emitter, 24...Oxide film (insulating layer), 26...
1st electrode, 28...2nd electrode, 32...3rd electrode
electrode.
Claims (1)
記半導体基板の表面層にベースを形成し、このベ
ースの内部にエミツタを形成して成る単一のトラ
ンジスタと、 前記半導体基板の表面を覆う絶縁層と、 この絶縁層上に形成された第１及び第２の抵抗
と、 前記第１及び第２の抵抗の一端に接続されてい
るとともに、前記絶縁層に形成された開口を通し
て前記ベースに接続された第１の電極と、 前記第２の抵抗の他端に接続されるとともに、
前記絶縁層に形成されている開口を通して前記エ
ミツタに接続された第２の電極と、 前記第１の抵抗の他端に接続される第３の電極
と、 を備えるとともに、前記半導体基板に対して一つ
の角部側の矩形領域に前記ベースを配置し、前記
角部側と対角線上の角部側に前記第３の電極を配
置し、前記ベースと前記半導体基板の一辺部との
間における領域に前記第１の抵抗、前記ベースと
前記半導体基板の他辺部との間における領域に前
記第２の抵抗を配置したトランジスタ装置であつ
て、 前記第１の電極は前記第１及び第２の抵抗の電
極形成部とその周囲部の前記絶縁層、第２の電極
は前記第２の抵抗の電極形成部とその周囲部の前
記絶縁層、前記第３の電極は前記第１の抵抗の電
極形成部とその周囲部の絶縁層に跨がつて設置し
たことを特徴とするトランジスタ装置。[Claims for Utility Model Registration] A semiconductor substrate having a rectangular planar shape, this semiconductor substrate forming the only collector, a base formed on the surface layer of the semiconductor substrate, and an emitter formed inside this base. a single transistor comprising: an insulating layer covering a surface of the semiconductor substrate; first and second resistors formed on the insulating layer; and a single transistor connected to one end of the first and second resistors. a first electrode connected to the base through an opening formed in the insulating layer; and a first electrode connected to the other end of the second resistor;
a second electrode connected to the emitter through an opening formed in the insulating layer; and a third electrode connected to the other end of the first resistor; The base is disposed in a rectangular region on one corner side, the third electrode is disposed on a corner diagonal to the corner side, and the region is between the base and one side of the semiconductor substrate. The transistor device includes the first resistor and the second resistor disposed in a region between the base and the other side of the semiconductor substrate, wherein the first electrode is located between the first and second resistors. The electrode forming part of the resistor and the insulating layer around it, the second electrode is the electrode forming part of the second resistor and the insulating layer around the surrounding part, and the third electrode is the electrode of the first resistor. A transistor device characterized in that the transistor device is installed so as to straddle a forming part and an insulating layer around the forming part.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1982150194U JPS5954960U (en) | 1982-10-02 | 1982-10-02 | Electrode structure of semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1982150194U JPS5954960U (en) | 1982-10-02 | 1982-10-02 | Electrode structure of semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5954960U JPS5954960U (en) | 1984-04-10 |
| JPH0440271Y2 true JPH0440271Y2 (en) | 1992-09-21 |
Family
ID=30333188
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1982150194U Granted JPS5954960U (en) | 1982-10-02 | 1982-10-02 | Electrode structure of semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5954960U (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5756211B2 (en) * | 1973-04-06 | 1982-11-29 | ||
| JPS5233261U (en) * | 1975-08-29 | 1977-03-09 | ||
| JPS53110465A (en) * | 1977-03-09 | 1978-09-27 | Nec Corp | Semiconductor device |
-
1982
- 1982-10-02 JP JP1982150194U patent/JPS5954960U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5954960U (en) | 1984-04-10 |
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