JPH0440344U - - Google Patents
Info
- Publication number
- JPH0440344U JPH0440344U JP8054390U JP8054390U JPH0440344U JP H0440344 U JPH0440344 U JP H0440344U JP 8054390 U JP8054390 U JP 8054390U JP 8054390 U JP8054390 U JP 8054390U JP H0440344 U JPH0440344 U JP H0440344U
- Authority
- JP
- Japan
- Prior art keywords
- initialization
- signal
- instruction
- write
- dram
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Dram (AREA)
Description
第１図は本考案を実施したＤＲＡＭ初期化回路
の実施例を表わす図、第２図は本考案回路の動作
を表わすフローチヤート、第３図はアドレス構成
図、第４図は従来のＤＲＡＭ初期化回路を表わす
図である。
１……４ＭＤＲＡＭ、２……メモリ・コントロ
ーラ、３……ＣＰＵ、４……アドレス・デコーダ
、５……フリツプ・フロツプ回路、６……論理和
回路。
Fig. 1 is a diagram showing an embodiment of a DRAM initialization circuit implementing the present invention, Fig. 2 is a flowchart showing the operation of the inventive circuit, Fig. 3 is an address configuration diagram, and Fig. 4 is a conventional DRAM initialization circuit. FIG. 1...4 MDRAM, 2...Memory controller, 3...CPU, 4...Address decoder, 5...Flip-flop circuit, 6...OR circuit.
Claims (1)
いて、ＣＰＵから送出される初期化指示により初
期化信号を出力する初期化信号生成部と、前記初
期化信号を書き込み指示信号としリフレツシユ指
令を待つてテスト・モードに移行し所定番地毎に
同一初期値データの書き込みを指示するメモリ・
コントローラとを備えることを特徴とするＤＲＡ
Ｍ初期化回路。 The DRAM initialization circuit that initializes the DRAM includes an initialization signal generation section that outputs an initialization signal in response to an initialization instruction sent from the CPU, and a test mode that uses the initialization signal as a write instruction signal and waits for a refresh instruction. memory that instructs to write the same initial value data for each predetermined location.
A DRA characterized by comprising a controller.
M initialization circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8054390U JPH0440344U (en) | 1990-07-27 | 1990-07-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8054390U JPH0440344U (en) | 1990-07-27 | 1990-07-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0440344U true JPH0440344U (en) | 1992-04-06 |
Family
ID=31625704
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8054390U Pending JPH0440344U (en) | 1990-07-27 | 1990-07-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0440344U (en) |
-
1990
- 1990-07-27 JP JP8054390U patent/JPH0440344U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6294498U (en) | ||
| JPH0440346U (en) | ||
| JPH0458761U (en) | ||
| JPS6421452U (en) | ||
| JPH01173788U (en) | ||
| JPH0246245U (en) | ||
| JPS5845586U (en) | display device | |
| JPS63171845U (en) | ||
| JPS6093200U (en) | Dynamic memory access circuit | |
| JPH03115998U (en) | ||
| JPH0366441U (en) | ||
| JPH0328595U (en) | ||
| JPH0420698U (en) | ||
| JPS61163400U (en) | ||
| JPS62101195U (en) | ||
| JPH0214149U (en) | ||
| JPH0452252U (en) | ||
| JPH03116446U (en) | ||
| JPS59130290U (en) | memory board | |
| JPS63118646U (en) | ||
| JPS61149198U (en) | ||
| JPS58140599U (en) | Dynamic random access memory control circuit | |
| JPS6413568U (en) | ||
| JPH03124398U (en) | ||
| JPS6311799U (en) |