JPH0452252U - - Google Patents

Info

Publication number
JPH0452252U
JPH0452252U JP9362190U JP9362190U JPH0452252U JP H0452252 U JPH0452252 U JP H0452252U JP 9362190 U JP9362190 U JP 9362190U JP 9362190 U JP9362190 U JP 9362190U JP H0452252 U JPH0452252 U JP H0452252U
Authority
JP
Japan
Prior art keywords
address
address information
select signal
start address
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9362190U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP9362190U priority Critical patent/JPH0452252U/ja
Publication of JPH0452252U publication Critical patent/JPH0452252U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例に係るメモリ制御装
置のブロツク図、第2図は従来のメモリ制御装置
のブロツク図である。 101……メモリユニツト、102……アドレ
ス入力ライン、103……スタートアドレスレジ
スタ、104……エンドアドレスレジスタ、10
5,106……コンパレータ、107……アンド
ゲート、108……セレクト信号ライン、109
……コントローラ、110……IDデータ、11
1……バツフア、112……データバス。
FIG. 1 is a block diagram of a memory control device according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional memory control device. 101...Memory unit, 102...Address input line, 103...Start address register, 104...End address register, 10
5, 106... Comparator, 107... AND gate, 108... Select signal line, 109
... Controller, 110 ... ID data, 11
1...Batsuhua, 112...Data bus.

Claims (1)

【実用新案登録請求の範囲】 スタートアドレス情報およびエンドアドレス情
報を記憶するアドレスレジスタと、 指定アドレスが前記スタードアドレスと前記エ
ンドアドレスとの間の範囲に含まれるときのみメ
モリユニツトにセレクト信号を出力するセレクト
信号発生回路と、 前記アドレスレジスタに前記スタートアドレス
情報およびエンドアドレス情報を書込むコントロ
ーラと、 を備えているメモリ制御装置。
[Claims for Utility Model Registration] An address register that stores start address information and end address information, and outputs a select signal to a memory unit only when a specified address is included in a range between the start address and the end address. A memory control device comprising: a select signal generation circuit; and a controller that writes the start address information and end address information to the address register.
JP9362190U 1990-09-06 1990-09-06 Pending JPH0452252U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9362190U JPH0452252U (en) 1990-09-06 1990-09-06

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9362190U JPH0452252U (en) 1990-09-06 1990-09-06

Publications (1)

Publication Number Publication Date
JPH0452252U true JPH0452252U (en) 1992-05-01

Family

ID=31830972

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9362190U Pending JPH0452252U (en) 1990-09-06 1990-09-06

Country Status (1)

Country Link
JP (1) JPH0452252U (en)

Similar Documents

Publication Publication Date Title
JPS6034648U (en) Memory paging system in microcomputer
JPH0452252U (en)
JPH022751U (en)
JPS618354U (en) Direct memory access device
JPS59118048U (en) Bidirectional direct memory access transfer circuit
JPS5851333U (en) Program processing device
JPS60640U (en) Parallel processing system for DMA processing and program measurement mode
JPH01173788U (en)
JPH02116346U (en)
JPS61164551U (en)
JPS6356451U (en)
JPS62125955U (en)
JPS63179548U (en)
JPH0181794U (en)
JPS63147740U (en)
JPH0466646U (en)
JPH0428346U (en)
JPS6439540U (en)
JPH0455646U (en)
JPH048154U (en)
JPS6173192U (en)
JPS5837267U (en) Video synthesis device
JPH01138143U (en)
JPS63138699U (en)
JPH0377544U (en)