JPH0440549U - - Google Patents

Info

Publication number
JPH0440549U
JPH0440549U JP7562390U JP7562390U JPH0440549U JP H0440549 U JPH0440549 U JP H0440549U JP 7562390 U JP7562390 U JP 7562390U JP 7562390 U JP7562390 U JP 7562390U JP H0440549 U JPH0440549 U JP H0440549U
Authority
JP
Japan
Prior art keywords
chip
area
periphery
active
convex
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7562390U
Other languages
Japanese (ja)
Other versions
JPH083008Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7562390U priority Critical patent/JPH083008Y2/en
Publication of JPH0440549U publication Critical patent/JPH0440549U/ja
Application granted granted Critical
Publication of JPH083008Y2 publication Critical patent/JPH083008Y2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Landscapes

  • Bipolar Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例のチツプの周辺部の
構造を示す断面図、第２図は従来のバイポーラ集
積回路チツプの一例の周辺部の構造を示す断面図
である。 １……凸状のチツプ周辺部の不活性領域、２…
…能動領域、３……絶縁膜、４……Ａｌ配線、な
お図中同一符号は同一または相当する部分を示す
。 FIG. 1 is a sectional view showing the peripheral structure of a chip according to an embodiment of the present invention, and FIG. 2 is a sectional view showing the peripheral structure of an example of a conventional bipolar integrated circuit chip. 1... Inactive area around the convex chip, 2...
. . . active region, 3 . . . insulating film, 4 . . . Al wiring, and the same reference numerals in the drawings indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] チツプの周辺部を除く全域を凹状にエツチング
し、エツチングした領域内に能動部分を形成する
ことで、チツプの周辺部に表面が内側の能動領域
表面より高い凸状の不活性領域を形成し、チツプ
の能動領域の部分に加わるモールド樹脂によるせ
ん断応力を軽減させたことを特徴とするバイポー
ラ集積回路装置。 By etching the entire area of the chip except for the periphery in a concave manner and forming an active part in the etched area, a convex inactive area is formed in the periphery of the chip, the surface of which is higher than the surface of the inner active area, A bipolar integrated circuit device characterized by reducing shear stress due to mold resin applied to the active region of a chip.
JP7562390U 1990-07-18 1990-07-18 Bipolar integrated circuit device Expired - Fee Related JPH083008Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7562390U JPH083008Y2 (en) 1990-07-18 1990-07-18 Bipolar integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7562390U JPH083008Y2 (en) 1990-07-18 1990-07-18 Bipolar integrated circuit device

Publications (2)

Publication Number Publication Date
JPH0440549U true JPH0440549U (en) 1992-04-07
JPH083008Y2 JPH083008Y2 (en) 1996-01-29

Family

ID=31616360

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7562390U Expired - Fee Related JPH083008Y2 (en) 1990-07-18 1990-07-18 Bipolar integrated circuit device

Country Status (1)

Country Link
JP (1) JPH083008Y2 (en)

Also Published As

Publication number Publication date
JPH083008Y2 (en) 1996-01-29

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees