JPH0441378Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a clock pulse generation circuit in a digital signal processing device, and particularly to a clock pulse generation circuit that can control the output clock frequency with high density.

[Prior Art] Conventionally, in the case of a clock pulse generation circuit for a digital signal processing device, the goal has been to make the phase of the clock pulse continuous and the frequency stable, and various efforts have been made to achieve this goal. It's here. As a result, many stable clock pulse oscillators have been developed today.

On the other hand, known literature: Otsuka, Ninomiya, "Feed forward type time base collector" (Television Society Technical Report, TEBS83-1, pages 1-6)
(September 27, 1981), a clock pulse generation circuit for a digitized signal processing device for television signals, which selectively changes the phase of the clock pulse for each horizontal synchronization period of an input television signal. A control method has been proposed.

[Problem to be solved by the invention] By the way, the example seen in this well-known document is one in which linear digitized signal processing technology is extended from only on the frequency axis to the time axis, and digital signal processing is Therefore, it can be noted that it was implemented in a more general manner.

However, in the above example, the clock pulse phase is only controlled for each horizontal period of the input television signal, and the frequencies of the clock pulses for each horizontal period are all the same.

Therefore, this invention proposes a clock pulse generation circuit devised with the aim of enabling more general digital signal processing than the previously known example, and which changes the period of the clock pulse for each pulse. It has been made possible to do so.

[Technical means for solving the problem] In order to solve the above-mentioned problem, this invention provides a clock pulse generation circuit for a digital signal processing device that has a continuous phase and a constant frequency over a long period of time. It has a pulse delay section in which a plurality of delay lines having a delay time of one period or less of a stable clock pulse signal are connected in series, and the clock pulse is applied to this pulse delay section, and the clock pulses are reciprocated by the delay time of the delay line. A number of clock pulse groups with different phases are formed, and from among these clock pulse groups, a clock pulse with a phase equal to that of the clock pulse output immediately before, or with a phase relationship before and after that phase, is formed at intervals approximately equal to the clock pulse period. a clock pulse selection section that selects and outputs one phase from the position of the clock pulse; a data latch section that determines information related to the next clock pulse phase to be output at the timing of the clock pulse that was output immediately before; The control data generating section sequentially generates information regarding the phase of the clock pulse to be output for each clock pulse output immediately before, and is characterized in that the period of the output clock pulse is changed for each pulse.

[Effect] By newly introducing the means of this invention,
Delay lines 12-1 used for each output clock pulse
4 delay time τ/8 (τ is one period of the basic clock)
It becomes possible to control the phase by that amount.

As a result, by changing the method of controlling the phase of each output clock pulse for each predetermined length unit determined for the input signal to be processed, it is possible to change the frequency of the output clock pulse for each predetermined length unit.

At this time, if the original clock pulse is obtained from a highly stable clock oscillator, precise frequency control becomes possible.

[Embodiment] Next, an example of a clock pulse generation circuit according to the present invention will be explained in detail with reference to FIG. 1 and subsequent figures.

FIG. 1 is a functional block diagram showing an example of its basic configuration.

In this invention, a clock pulse (basic clock) obtained from a stable clock pulse oscillator (not shown) is used, and for each predetermined length unit arbitrarily determined for the input signal to be processed, a clock pulse related to the frequency of the clock pulse required by that unit is used. information is input.

Then, the phase is controlled for each pulse, and when the clock pulse frequency is measured for each predetermined length unit, a clock pulse controlled to the necessary frequency for the predetermined length unit is output.

For this purpose, in this invention, as shown in FIG.
0, data latch section 30 and control data generation section 4
Consists of 0.

In the pulse delay unit 10, with respect to the input clock,
n pulses are formed which are sequentially out of phase by τ/n.

Here, τ is one period of the input clock, and n is an integer. In this example, n=8.

The clock pulse selection section 20 selects a clock pulse having necessary phase information from among the n clock pulses. Which phase of the clock pulse is selected is determined by the frequency information supplied to the control data generator 40.

The data latch section 30 forms address data of the clock pulse to be selected from this frequency information and the phase of the output clock pulse.

Next, the detailed configuration and operation of each of the above-mentioned parts will be explained with reference to FIG. 2 and subsequent figures.

FIG. 2 is an explanatory diagram showing a detailed configuration example of each part.

In this example, the unit of phase control of the output clock pulse in FIG. 1 is 1/8 of one clock pulse period τ.

A stable clock pulse is first input to a pulse delay section 10. In the pulse delay section 10, the clock pulse passes through a buffer amplifier 11 and then passes through three continuously connected delay lines 12 having a delay amount of τ/8.
.about.14 is supplied to the first stage delay line 12.

Buffer amplifier 11 is used for the purpose of buffering the clock pulse oscillator.

Here, if the clock pulse a of the buffer amplifier 11 is the basic clock, each delay line 12 to 14
The relative relationships with the clock pulses b to d obtained from the above are shown in FIGS. 3A to 3D. That is,
Clock pulses a~ whose phases are shifted by τ/8
d is obtained.

These clock pulses a to d are supplied to inverters 15 to 18, which also function as buffers, respectively, and their phases are inverted.

Assuming that the phase-inverted clock pulses are e to h, these eight clock pulses a to h are pulses whose phase is sequentially shifted by τ/8 with respect to the reference phase of the basic clock, as shown in FIG. obtained as.

These clock pulses a to h are led to a clock pulse selection section 20. Clock pulse selection section 2
0, a general data multiplexer can be used.

Address data indicating which clock pulse to select from among clock pulses a to h is also input to the clock pulse selection section 20. This address data is determined by the data latch section 30 based on the timing of the clock pulse output immediately before.

In this example, since the unit of phase control of the output clock pulse is .tau./8, the number of addresses is 8, and therefore the address data consists of 3 bits.

Therefore, these address data are encoded, for example, as shown in FIG. 4, corresponding to the phases of clock pulses a to h in FIG.

The data latch section 30 has a latch circuit 31 for address data, and a clock pulse output immediately before (an output clock pulse obtained at a terminal 39).
A pulse delayed using a delay line 33 having a delay amount of τ/2 is supplied to the latch circuit 31 as a latch clock. This finalizes the address data.

Using the lower two bits of the determined address data (latch data), the clock pulse selection section 20 selects the phases of the clock pulses a to h. The output clock pulse and the most significant bit of the address data are then supplied to an exclusive OR operator (exclusive OR circuit) 32. Therefore, (1) when the most significant bit is "L", the clock pulse of the clock pulse selection section 20 is passed through as is; (2) when the most significant bit is "H", the clock pulse in (1) is inverted.

The clock pulse thus obtained passes through the AND circuit 34 and becomes the output clock pulse.

Here, the other input pulse x of the AND circuit 34 is a control signal for keeping the output clock pulse at "L" for at least the time required from the determination of the address data of the clock pulse selection section 20 to the determination of the output, and is as follows.

For example, the phase of the clock pulse that was output just before is D in Figure 3, and the phase that should be output next is E in the same figure.
Consider the case where .

The address data of clock pulse e is latched at time t1 in FIG. At that moment, the address data changes from "011" to "100", so the output of the exclusive OR circuit 32 is inverted. Therefore, the output of the exclusive OR circuit 32 remains at "H" (FIGS. 5A to 5E).

Then, from time t1, the clock pulse selection section 2
Time t2 after the time required to determine the output of 0
Then, the clock pulse selection section 20 selects the clock pulse a selected by the lower two bits of the address.
is output.

As a result, the output of the exclusive OR circuit 32 becomes "L", and a clock pulse e, which is an inversion of the clock pulse a, is output until time t3 when the next address data is latched by the clock pulse e (see E in the figure).

Clock pulse selection section 2 obtained through the above process
The zero output has a significant distortion in symmetry, as shown in FIG. 5E. The AND circuit 34 is provided for the purpose of correcting this distortion.

That is, the input pulse x is at least at time t1
The signal is made to be "L" during the period from t2 to t2. By calculating the AND of the input pulse x and the output of the exclusive OR circuit 32 in the AND circuit 34, the output clock shown in FIG. 5I is obtained.

Therefore, the clock used to latch the latch circuit 31 is delayed by a delay line 36 with a delay amount of t1 to t2 or more and τ/2 or less, and the same clock is inverted by an inverter 37, and the same delay pulse as before is used. An input pulse x is created by calculating the above with a negative logic AND circuit 38. These timing relationships are shown in FIGS. 5F-H.

Incidentally, the address data input to the latch circuit 31 needs to be generated from the control data generator 40 between the timing of the clock pulse output immediately before and at least the latch timing of the latch circuit 31.

The control data generating section 40 that satisfies this condition can have various configurations.

For example, the simplest way is as shown in Figure 2.
It can be composed of a ROM 41 and an address counter 42. In this case, the ROM 41 stores frequency information necessary for each predetermined length unit of the input signal to perform processing to control the clock frequency as a row address, and information that increases according to the output clock pulse as a column address. Added.

Column addresses are generated sequentially by counter 42 in accordance with output clock pulses. The counter 42 is cleared every predetermined length unit of the input signal to be processed, and the column address is sequentially increased after returning to 0.

Each address in the ROM 41 is composed of 3 bits, and address information regarding the phase of the clock pulse to be output next is written in advance. By setting this write information in correspondence with the row address (frequency information), the clock pulse frequency in units of the predetermined length can be controlled as desired.

The control data generating section 40 can also be configured as shown in FIG. In FIG. 6, the address information input to the latch circuit 31 is generated by a 3-bit counter 43.

At this time, the frequency of the output clock pulse can be controlled to be low or high by counting up or down the count of the counter 43.

The change in frequency of the output clock pulse can be set to be large or small depending on whether the clock used for counting by the counter 43 is generated every output clock pulse or every few clocks.

The ROM 44 controls the above operations according to frequency information necessary for each predetermined length.

That is, this ROM 44 is supplied with frequency information as its address data, and this ROM 44 is supplied with frequency information as its address data.
4 outputs information related to count up/down and information related to the generation of clock pulses used for counting by the counter 43.

Of these, the former is directly supplied to the counter 43. The latter, on the other hand, is added to a counter 45 clocked by the output clock pulse. The counter 45 repeatedly counts the number of data obtained from the ROM 44, and generates a count end pulse each time the count ends.

This end-of-count pulse is used as a clock for counter 43, allowing it to perform the operations described above.

That is, the data written in advance in the ROM 44 in accordance with the frequency information is the predetermined setting data for the counter 45, which indicates how many clocks the counter 45 should generate a count end pulse. The initial setting data is stored in the counter 4 for each predetermined length unit.
It is set at 5.

In the configuration of FIG. 6, in addition to the operation related to the frequency change described above, the desired phase of the output clock pulse can be shifted with respect to the basic clock.

The desired phase data is set in each predetermined length unit by the counter 43, and this data is stored in the ROM.
The signal is guided to the latch circuit 31 in a form weighted with the frequency data of 44.

It should be noted that the phase shift by providing initial phase data is an example in which this invention can be used for the same purpose as in the previous known document.

Further, if a plurality of sets of counters 43 and 45 are used and these sets are sequentially switched each time a count end pulse is generated, it is possible to finely control the cycle of count end pulse generation.

In this case, since the counting status of the counter 43 can be set in detail, it goes without saying that the frequency control accuracy of the output clock pulse can be improved.

Note that when the control data generating section 40 is configured as shown in FIG. 2, the hardware configuration is simple but requires a large capacity ROM, and when the control data generating section 40 is configured as shown in FIG. 6, the hardware configuration is simple. Although it is complicated, the ROM has a small capacity and good features.

Therefore, it is considered appropriate to use the former when the predetermined length unit is a relatively short output clock pulse cycle, and the latter when the predetermined length unit is relatively long.

[Effect of the invention] As explained above, in this invention, since the phase of the clock pulse can be changed for each clock pulse, the frequency of the clock pulse can be changed independently for each predetermined length unit determined for the input signal to be processed. can be changed.

In this case, this invention provides a means to control the phase frequency of the clock pulse from a single stable oscillator as needed, which is completely different in principle and result from a method of controlling the clock pulse frequency using a PLL or the like. I can do it.

Therefore, this invention has the unique effect of opening up new possibilities of performing signal processing on the time axis using digital signal processing technology.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram showing an example of the basic configuration of this invention, FIG. 2 is an explanatory diagram showing a detailed configuration example of each part, FIG. 3 is a diagram conceptually explaining a clock pulse group, and FIG. FIG. 5 is a diagram showing the relationship between clock pulse groups and encoding, FIG. 5 is an explanatory diagram showing the timing relationship related to clock pulse selection, and FIG. 6 is a block diagram showing another example of the configuration of the control data generating section. 10... Pulse delay section, 20... Clock pulse selection section, 30... Data latch section, 40... Control data generation section.

Claims (1)

[Claims for Utility Model Registration] A clock pulse generation circuit for a digital signal processing device, which has multiple delays having a delay time of one period or less of a clock pulse signal whose phase is continuous over a long period of time and whose frequency is stable. The clock pulse is applied to the pulse delay section to form a plurality of clock pulse groups having mutually different phases by the delay time of the delay line, and these clock pulse groups a clock pulse selection section that selects and outputs one phase from among the clock pulse positions that have the same phase as the clock pulse output immediately before, or that are located in a phase relationship before and after the relevant phase, at intervals approximately equal to the clock pulse period; a data latch unit that determines information related to the clock pulse phase to be output next at the timing of the clock pulse output immediately before; and a data latch unit that determines information related to the phase of the clock pulse to be output next at the timing of the clock pulse output immediately before; 1. A clock pulse generating circuit comprising: a control data generating section that generates sequentially; and a clock pulse generating circuit that changes the period of an output clock pulse for each pulse.