JPH0441492B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor device that constitutes an image display device or the like by combining with an optical element such as a liquid crystal or an EL, and a method for manufacturing the same.

Conventional configuration examples and their problems Amorphous silicon, which is formed by containing several percent of hydrogen or fluorine in its composition to compensate for imperfections in atomic bonding pairs, can be formed at low temperatures. It is attracting attention as a semiconductor material for producing low-cost solar cells because it can be easily made into a large area. However, compared to single-crystal silicon, the free electron mobility is 0.1 to 1 cm ² /V·sec, which is more than three orders of magnitude smaller, making it impossible to obtain a semiconductor device with performance worthy of integration. Even so, it is possible to obtain a switching array of insulated gate type (MIS) transistors that do not require high-speed operation or large operating currents and constitute an image display device by combining them with, for example, a liquid crystal cell.

However, in MIS transistors that have become known in literature, the source/drain electrodes and the gate metal layer are not in a self-aligned positional relationship, and are connected to the source or drain through the gate-source or gate-drain overlap capacitance. The potential of the liquid crystal cell, which is the load, turns on the MIS transistor.
There was a drawback that the gate pulse applied to turn off the device fluctuated at the rise and fall times. If you introduce an auxiliary capacitor that overlaps in parallel with the liquid crystal cell and is larger than the capacitor to stabilize the potential, a large on-current and a long write time will be required to charge the auxiliary capacitor, and in the former case, the large mobility will be reduced by the amorphous This is equivalent to what is required for high-quality silicon, and is currently difficult to achieve, and the latter also means that it is not possible to set a large number of scanning lines. For this reason, the above-mentioned image display device has a liquid crystal cell as large as 1 mm square, and the number of picture elements is as small as 20×20, but it is currently not available. The inventors of the present invention have already proposed a self-aligned MIS transistor and have achieved excellent results despite the problems mentioned above, but this example will be explained first here.

FIG. 1 and FIGS. 2a to 2d are a plan view of the above-mentioned MIS transistor and a sectional view of the manufacturing process taken along line A-A' in FIG. 1, and the manufacturing process is as described below.

First, as shown in FIG. 2a, a first amorphous silicon layer 2 containing no impurities as a donor or acceptor, for example, a first amorphous silicon layer 2 made of silicon nitride, is formed on an insulating substrate 1 made of, for example, a glass plate. An insulating layer 3, a first metal layer 4 of for example molybdenum and a thin film layer 5 of for example aluminum are applied successively over the entire surface. At this time, contamination caused by depositing the first insulating layer 3 can be avoided without exposing the amorphous silicon layer 2 to the atmosphere, and the characteristics of the MIS transistor are stabilized. This is effective for strengthening the adhesion of the first insulating layer 3. For this purpose, it is easy to deposit plastic material by glow discharge of silane gas, and in the same chamber,
This is preferably carried out using a vacuum conveyance path and a plurality of chambers.

Next, as shown in FIG. 2b, the first thin film layer 5'
After selectively exposing the amorphous silicon layer 2 by forming a laminated layer consisting of the metal layer 4' and the first insulating layer 3', a second amorphous silicon layer containing impurities to serve as donors or acceptors is formed on the entire surface. A layer of silicon 6 is deposited. Then, as shown in FIG. 2c, the first and second amorphous silicon layers including the laminated portion are formed into island shapes 2' (portions indicated by broken lines in FIG. 1) and 6', and then heated. Place in phosphoric acid. Then, since the laminated portion is as thick as 6000 to 9000 Å, if the amorphous silicon layer 6' is as thin as 1000 to 2000 Å, the amorphous silicon layer 6' will break at the stepped portion 7 of the laminated portion. Since a part or all of the side surface of the layer 5' is exposed, the thin film layer 5' made of aluminum is dissolved, and at the same time, the amorphous silicon layer containing impurities on the thin film layer 5' is also removed and becomes a gate electrode. The first metal layer 4' is exposed.

Thereafter, the entire surface is covered with a second layer made of silicon nitride, for example.
An insulating layer 8 is deposited, openings 9 and 10 are formed on the amorphous silicon layer 6' and the gate metal layer 4', and source/drain wiring made of, for example, aluminum is formed through the openings 9 and 10. 11,12
Then, the gate lead wiring 13 is formed to complete the MIS transistor. The second amorphous silicon layer 6' containing impurities formed on the first amorphous silicon layer 2' containing no impurities serves as the source/drain 1.
Needless to say, it constitutes 4 and 15.

The MIS transistor shown in FIGS. 1 and 2 is formed in a self-aligned manner with the source/drain and gate, as in most single-crystal silicon MOS transistors. That is, the end of the gate metal layer 4' and the end of the source/drain 14, 15 are on the same straight line, and there is no planar overlap between them. This is because the source and drain are made of amorphous silicon containing impurities, and the deposition method is lift-off using a gate pattern. Therefore, the capacitance between the gate and source or between the gate and drain is reduced to 1/10 to 1/100 compared to a non-self-aligned type.
It has the advantage that constraints on pulse operation are significantly relaxed, and reliability is also excellent because the channel portion is isolated from the outside air due to the presence of the second insulating layer 8.

However, since the amorphous silicon layer and the gate insulating layer must be formed continuously, and lift-off using the gate pattern is adopted, the following restrictions are imposed. Figure 2 e and f are the first
In the cross-sectional views taken along the lines B-B' and C-C' in the figure, an amorphous silicon layer 2' containing no impurities and a gate insulating layer 3' are formed between the gate metal layer 4' and the insulating substrate 1. Existing. Therefore, as shown in FIG. 2f, at the intersection of the source wiring 11 and the gate metal layer 4', the step of the stacked layer consisting of the amorphous silicon layer 2', the gate insulating layer 3', and the gate metal layer 4' becomes large. As a result, the coverage of the second insulating layer 8 deteriorates, and the source wiring 11 may be broken or the source wiring 11 may be broken.
There is a possibility that the insulation between the gate metal layer 4' and the gate metal layer 4' will deteriorate. If an attempt is made to improve the coverage by increasing the thickness of the second insulating layer 8, the opening 10 will be Since the difference in level becomes large and the gate wiring 13 is inconveniently broken, the gate wiring 13 must be made thicker, which makes microfabrication difficult.

Furthermore, in the MIS transistor, the source/drain wiring is exposed, so when used in combination with a liquid crystal or EL, it is necessary to introduce a new insulating layer to separate it from them. At least the source wiring 11, which also serves as the video signal line, must be insulated with an insulating layer, otherwise the source wiring 11 will be LCD or EL.
Since it drives directly, matrix display becomes impossible. It is clear that when a new insulating layer is deposited, if the source/drain wirings 11 and 12 are thick, various problems due to coverage will occur.

Purpose of the Invention The present invention has been made in view of the above situation, and it is possible to arrange a large number of semiconductor switch elements in a two-dimensional matrix and use the same number of picture elements in a semiconductor device, etc. that constitutes an image display device in combination with a liquid crystal or EL. It is an object of the present invention to provide a semiconductor device having an insulating layer suitable for forming a picture element portion while forming a good multilayer wiring at the above-mentioned intersections.

Structure of the Invention In the MIS type transistor of the present invention, a first metal layer serving as source/drain wiring is formed on an insulating substrate, and a metal layer mainly composed of silicon is formed on the insulating substrate via the first insulating layer. An island-shaped first non-single crystal semiconductor layer is deposited, and a laminated portion consisting of a second insulating layer and a second metal layer serving as a gate electrode is formed on a portion of the first non-single crystal semiconductor layer. formed so as to connect a region other than the second insulating layer on the first non-single crystal semiconductor layer and the first metal layer through an opening formed in the first insulating layer. A secondary material whose main component is silicon and contains impurities that serve as donors or acceptors.
The invention is characterized in that the non-single-crystal semiconductor layer is used as a source and drain, and a third metal layer is formed on a third insulating layer deposited on the entire surface. Let's discuss an example. Note that parts with the same functions are given the same numbers as in Figures 1 and 2.

DESCRIPTION OF EMBODIMENTS FIG. 3 shows a plan view of a semiconductor device according to an embodiment of the present invention, and FIGS.
It is a sectional view of the manufacturing process along the line A', and the manufacturing process is as described below.

First, as shown in FIG. 4a, source/drain wiring 1 made of, for example, molybdenum is placed on a glass plate 1
1 and 12, and then a third insulating layer 16 made of silicon oxide, for example, and a first insulating layer 16 that does not contain impurities.
An amorphous silicon layer 2 , the aforementioned first insulating layer 3 made of silicon nitride, for example, a first metal layer 4 made of molybdenum, for example, and a thin film layer 5 made of aluminum, for example, are successively deposited over the entire surface. At this time, the first layer is heated without exposing the amorphous silicon layer 2 to the atmosphere.
As already mentioned, favorable results can be obtained by depositing an insulating layer 3 of .

Next, as shown in FIG. 4b, a laminated portion consisting of a thin film layer 5', a first metal layer 4' and a first insulating layer 3' is formed to expose the amorphous silicon layer 2, and then the laminated portion is laminated. Then, an opening 17 is formed in the third insulating layer 16 to expose a part of the source/drain wirings 11 and 12.

Then, as shown in FIG. 4C, a second amorphous silicon layer 6 containing an impurity serving as a donor or acceptor is deposited on the entire surface, and the opening 17 is formed on the island-shaped amorphous silicon layer 2'. A second amorphous silicon layer 6' is formed to connect the source/drain wirings 11 and 12 via the second amorphous silicon layer 6'. Thereafter, as described above, the thin film layer 5' is removed and the second amorphous silicon layer on the thin film layer 5' is selectively removed to expose the gate metal layer 4', as shown in FIGS. A second insulating layer 8 made of silicon nitride, for example, is deposited as shown;
An opening 10 is formed in the second insulating layer 8 on the gate metal layer 4', and an opening 18 penetrating the third insulating layer 16 and the second insulating layer 8 is formed above the source wiring 11.
, and the gate metal layer 4' is formed through the opening 10.
Furthermore, a gate lead-out wire 13 and a source lead-out wire 19 made of, for example, aluminum and connected to the source wire 11 through the opening 18 are formed to complete the semiconductor device according to the present invention. In order to obtain a liquid crystal image display device, glass substrates 20 on which transparent electrodes are formed may be placed facing each other, and liquid crystal 23 may be sealed between them. 4e, f, and g are cross-sectional views of the semiconductor device of FIG. 3 (substrate 20, electrode 21, and liquid crystal 22 are not shown) along lines B-B', CC', and D-D', Gate wiring extraction part and gate wiring 4' respectively
This corresponds to the intersection between the source wire 11 and the source wire 11, and the source wire extraction portion.

As can be seen from the comparison between FIG. 2 f and FIG. 4 f, in FIG. Whereas the source wiring 11 was formed on the thicker gate wiring layer 4' with the second insulating layer 8 interposed therebetween, in the present invention, a film insulated by the third insulating layer 16 is formed. Since the thin source wiring 11 with a thickness of 1000 to 1500 Å passes under the gate wiring layer 4' via the first amorphous silicon layer 2' and the first insulating layer 3', multilayer The effective level difference at wiring intersections is reduced. As a result, there are no disconnections at the intersections of the multilayer wiring, and the dielectric strength is significantly improved.

Comparing FIG. 2e and FIG. 4e, there is no improvement in the gate wiring lead-out part, and in the source wire lead-out part in FIG. It can be seen that the source lead-out wiring 19 must be formed through the opening 18, and that step breakage is likely to occur at the step of the opening 18. However, in a semiconductor device that constitutes an image display device, only the pixel portion requires microfabrication, and it is sufficient to have one gate wiring extraction portion and one source wiring extraction portion for each pixel pitch, so the processing accuracy is It becomes much looser. Therefore, the gate lead-out wiring 13 and the source lead-out wiring 19
There is no problem even if the film is thick. If the video signal and the scanning signal are supplied from the outside, for example, by wire bonding, there will be no problem even if a step break occurs at the step portions of the openings 10 and 18.

It can be seen that these characteristics are unique to the semiconductor device constituting the image display device, and cannot be realized with a configuration in which the source/drain wirings 11 and 12 are formed simultaneously with the gate lead wiring 13 as in the conventional example.

In the semiconductor device according to the present invention, the pixel portion is protected by the second insulating layer 8, so even if the liquid crystal is aligned and polished with a cloth, there will be no damage caused by the generation of metal powder. Moreover, since no chemical reaction occurs due to chemicals or heating, excellent effects were obtained, such as being extremely advantageous when attaching EL elements and the like. It goes without saying that MIS transistors are now self-aligned.

Note that the present invention can also be applied to silicon materials other than single crystal silicon, ie, microcrystalline silicon and polycrystalline silicon.

Effects of the Invention As described above, the present invention reduces the effective step difference at the intersection of multilayer wiring, prevents step breakage, and
It is possible to obtain a semiconductor device suitable for image display, etc., which has a significantly improved dielectric strength voltage and is less susceptible to surface damage.

[Brief explanation of drawings]

FIG. 1 is a schematic plan view of an MIS transistor with a conventional configuration, FIGS. 2 a to d are cross-sectional views of the manufacturing process along line A-A' of the transistor in FIG.
f is a sectional view on line B-B', C-C' in Figure 1,
The figure is a schematic plan view of a semiconductor device according to an embodiment of the present invention, and FIGS. 4a to 4d are A-A of the semiconductor device of FIG.
A cross-sectional view of the manufacturing process along the line A', d is a partial cross-sectional view of the liquid crystal display device, Figures 4 e to g are B-B' in Figure 3,
FIG. 3 is a cross-sectional view of the display device taken along lines C-C' and D-D'. DESCRIPTION OF SYMBOLS 1... Insulating substrate, 2, 2'... First non-single crystal semiconductor layer, 3, 3'... First insulating layer, 4, 4'...
...Gate metal layer, 6, 6'... Second non-single crystal semiconductor layer, 8... Second insulating layer, 11, 12... Source/drain wiring, 13... Gate extraction wiring,
14, 15... Source/drain wiring, 16...
Third insulating layer, 18...source extraction wiring.

Claims (1)

[Claims] 1. A first metal layer serving as source/drain wiring is formed on an insulating substrate, and an island-shaped metal layer mainly composed of silicon is formed on the insulating substrate via the first insulating layer. a first non-monocrystalline semiconductor layer is deposited;
A laminated portion consisting of a second insulating layer and a second metal layer serving as a gate electrode is formed on a part of the non-single-crystal semiconductor layer of the second non-single-crystal semiconductor layer. A first metal layer containing silicon as a main component and containing an impurity serving as a donor or acceptor is formed so as to connect a region other than the insulating layer with the first metal layer through an opening formed in the first insulating layer. 1. A semiconductor device characterized in that a second non-single crystal semiconductor layer serves as a source and a drain, and a third metal layer is formed on a third insulating layer deposited over the entire surface. 2. A step of selectively forming a first metal layer to serve as source/drain wiring on an insulating substrate, and a step of forming a first insulating layer, a first non-single crystal semiconductor layer mainly composed of silicon, and a first metal layer on the entire surface. 2 insulating layer, a second metal layer,
a step of sequentially forming the second metal layer, the second non-single-crystal semiconductor layer containing impurities, and a thin film layer using a different etching agent; selectively forming a laminated portion;
forming the first non-single crystal semiconductor layer in an island shape; forming an opening in the first insulating layer to expose a part of the first metal layer; a step of forming a second non-single crystal semiconductor layer containing an impurity as a donor or an acceptor over the entire surface; and a step of connecting the island-shaped first non-single crystal semiconductor layer and the first metal layer. a step of selectively leaving the second non-single crystal semiconductor layer; a step of selectively removing the second non-single crystal semiconductor layer on the thin film layer along with the removal of the thin film layer; and a step of selectively removing the second non-single crystal semiconductor layer on the thin film layer; forming an opening in a third insulating layer on the second metal layer and first and third insulating layers on the first metal layer; A method for manufacturing a semiconductor device, comprising the step of selectively forming a third metal layer on the third insulating layer to be connected to the first or second metal layer via the third metal layer. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the second insulating layer is continuously formed without exposing the first non-single crystal semiconductor layer to the atmosphere.