JPH0441494B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an insulated gate MIS transistor, particularly an amorphous silicon MIS transistor and a manufacturing method for its integration.

Conventional structure and its problems Amorphous silicon, which is formed by containing several percent of hydrogen or fluorine in its composition to compensate for imperfections in atomic bonding pairs, can be formed at low temperatures. It is attracting attention as a semiconductor material for producing low-cost solar cells because it can be easily made into a large area. However, compared to single-crystal silicon, the free electron mobility is 0.1 to 1 cm ² /V·sec, which is more than three orders of magnitude smaller, and in a general sense, a semiconductor element with performance worthy of integration cannot be obtained. However, it does not require high-speed operation or large operating current. For example, by combining it with a liquid crystal cell, it is possible to obtain a switching array of insulated gate MIS transistors constituting an image display device.

However, it is well known in the literature that in MIS transistors, the source/drain electrodes and the gate metal layer are not in a self-aligned positional relationship, and the load is connected to the source or drain through the gate-source or gate-drain overlap capacitance. The potential of a certain liquid crystal cell turns on the MIS transistor.
There was a drawback that the gate pulse applied to turn off the device fluctuated at the rise and fall times. If you introduce an auxiliary capacitor that overlaps in parallel with the liquid crystal cell and is larger than the capacitor to stabilize the potential, a large on-current or a long writing time will be required to charge the auxiliary capacitor, and in the former case, the large mobility will be reduced by the amorphous This is equivalent to what is required for high-quality silicon, and is currently difficult to achieve, and the latter also means that it is not possible to set a large number of scanning lines. For this reason, the image display device described above has a large liquid crystal cell size of 1 mm square, and the number of picture elements is currently only available on a small scale of about 20×20. The present inventors have already proposed a self-aligned MIS transistor and have achieved excellent results, including solving the above-mentioned problems, but we will first explain this example here.

FIG. 1 and FIGS. 2a to 2d are a plan view of the above-mentioned MIS transistor and a sectional view of the manufacturing process along line A-A' in FIG. 1, and the manufacturing process is as described below.

First, as shown in FIG. 2a, on an insulating substrate 1 made of, for example, a glass plate, a first amorphous silicon layer 2 containing no impurities to serve as a donor or acceptor, a first insulating layer made of, for example, silicon nitride, is formed. A layer 3, a first metal layer 4, for example of molybdenum, and a thin film layer 5, for example of aluminum, are applied successively over the entire surface. At this time, if the first insulating layer 3 is deposited without exposing the amorphous silicon layer 2 to the atmosphere, contamination can be avoided and the characteristics of the MIS transistor will be stabilized. This is effective by strengthening the adhesion of the insulating layer 3. For this purpose, plasma deposition using glow discharge of silane-based gas is simple and can be done in the same chamber.
This is preferably carried out using a vacuum conveyance path and a plurality of chambers.

Next, as shown in FIG. 2b, the first thin film layer 5'
After selectively exposing the amorphous silicon layer 2 by forming a laminated portion consisting of the metal layer 4' and the first insulating layer 3', a donor or acceptor is formed over the entire surface as shown in FIG. 2c. A second amorphous silicon layer 6 containing impurities is deposited, and the first amorphous silicon layer 6 including the laminated portion is deposited.
and a second amorphous silicon layer in the form of an island 2' (first
(portions indicated by broken lines in the figure), 6' and then left in hot phosphoric acid. Then, the laminated part
Since it is thick at 6000 to 9000 Å, if the amorphous silicon layer 6' is thin at 1000 to 2000 Å, the stepped portion 7 of the laminated portion
As a result, the amorphous silicon layer 6' is broken and a part or all of the side surface of the thin film layer 5' is exposed, so the thin film layer 5' made of aluminum is dissolved, and at the same time, the impurities on the thin film layer 5' are removed. The amorphous silicon layer contained therein is also removed to expose the first metal layer 4' which will become the gate electrode.

Thereafter, as shown in FIG. 2d, a second insulating layer 8 made of silicon nitride, for example, is deposited on the entire surface.
Openings 9 and 10 are formed on the amorphous silicon layer 6' and the gate metal layer 4', and the openings 9 and 10 are
0 and a source made of aluminum, for example.
Drain wiring 11, 12 and gate lead wiring 1
3 to complete the MIS transistor. It goes without saying that the second amorphous silicon layer 6' containing impurities formed on the first amorphous silicon layer 2' containing no impurities constitutes the source trains 14 and 15.

In the MIS transistor shown in FIGS. 1 and 2, the source, drain, and gate are formed in a self-aligned manner, as in most single-crystal silicon MOS transistors. That is, the end of the gate metal layer 4' and the end of the source/drain 14, 15 are on the same straight line, and there is no planar overlap between them. This is because the source and drain are made of amorphous silicon containing impurities, and the deposition method is lift-off using a gate pattern. As a result, the capacitance between the gate and source or between the gate and drain is reduced to 1/10 to 1/100 compared to a non-self-aligned type, significantly easing restrictions on pulse operation, and Due to the presence of the insulating layer 8, the channel portion is isolated from the outside air, which has advantages such as excellent reliability.

However, since the amorphous silicon layer and the gate insulating layer must be formed continuously, and lift-off using the gate pattern is adopted, the following restrictions are imposed. Figure 2 e and f are the first
In the cross-sectional views taken along the lines B-B' and C-C' in the figure, an amorphous silicon layer 2' containing no impurities and a gate insulating layer 3' are formed between the gate metal layer 4' and the insulating substrate 1. Existing. Therefore, at the intersection of the source wiring 11 and the gate metal layer 4' as shown in FIG. As a result, the coverage of the second insulating layer 8 deteriorates, and the source wiring 11 may be broken or the source wiring 11 may be broken.
There is a possibility that the insulation between the gate metal layer 4' and the gate metal layer 4' will deteriorate. If an attempt is made to improve the coverage by increasing the thickness of the second insulating layer 8, the opening 10 will be Since the difference in level becomes large and the gate wiring 13 is inconveniently broken, the gate wiring 13 must be made thicker, which makes microfabrication difficult.

OBJECTS OF THE INVENTION The present invention was made in view of the above situation, and an object of the present invention is to provide good multilayer wiring in a semiconductor device or the like in which a large number of MIS transistors made of amorphous silicon are arranged.

Structure of the Invention In the MIS type transistor of the present invention, a first metal layer serving as source/drain wiring is formed on an insulating substrate, and a metal layer mainly composed of silicon is formed on the insulating substrate via the first insulating layer. An island-shaped first non-single-crystal semiconductor layer is formed, and a laminated portion consisting of a second insulating layer and a second metal layer that becomes a gate electrode is formed on a portion of the first non-single-crystal semiconductor layer. The second non-single-crystal semiconductor layer, which is mainly composed of silicon and contains impurities that serve as donors or acceptors, is deposited on the first non-single-crystal semiconductor layer in a region other than the second insulating layer. A third insulating layer having an opening including the first metal layer and the source/drain is formed, a third insulating layer including the opening and connecting the first metal layer and the source/drain. It is characterized in that a metal layer is formed.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that parts with the same functions are given the same numbers as in FIGS. 1 and 2.

FIG. 3 shows a plan view of a MIS transistor according to an embodiment of the present invention, and FIGS. 4 a to 4 d are sectional views of the manufacturing process along line A-A' in FIG. 3, and the manufacturing process is as described below. It is.

First, as shown in FIG. 4A, source/drain wirings 11 and 12 made of, for example, molybdenum are formed, and then a third insulating layer 16 made of, for example, silicon oxide, and a first amorphous silicon layer containing no impurities are formed. Layer 2, for example the aforementioned first layer of silicon nitride;
An insulating layer 3, a first metal layer 4 made of, for example, molybdenum, and a thin film layer 5, made of, for example, aluminum, are successively applied over the entire surface. As already mentioned, preferable results can be obtained if the first insulating layer 3 is deposited without exposing the amorphous silicon layer 2 to a contaminating atmosphere such as the atmosphere.

Next, as shown in FIG. 4B, a laminated portion consisting of the thin film layer 5', the first metal layer 4' and the first insulating layer 3' is formed to expose the amorphous silicon layer 2.

Then, as shown in FIG. 4C, a second amorphous silicon layer 6 containing an impurity serving as a donor or acceptor is deposited on the entire surface, and an island-shaped amorphous silicon layer 2' including the laminated portion is formed. (portions indicated by broken lines in FIG. 3), 6' are formed. Thereafter, as described above, the thin film layer 5' is removed and the second amorphous silicon layer on the thin film layer 5' is selectively removed to expose the second metal layer 4'.

Finally, as shown in FIGS. 4d and 4e, a second insulating layer 8 made of silicon nitride, for example, is deposited over the entire surface, and an opening 10 is formed in the second insulating layer 8 on the gate metal layer 4'. Then, an opening 9 penetrating the second and third insulating layers 8 and 16 including the source drains 14 and 15 and the source and drain wirings 11 and 12 is formed. The gate metal layer 4' is connected to the gate metal layer 4' through the opening 10 as a gate lead wiring 13, and the source/drain 14, 15 and the source/drain wiring 11, 12 are connected within the opening 9 including the opening 9. Metal wiring, which becomes the connection wiring 17 and 18, is formed using aluminum, for example, and the MIS transistor according to the present invention is completed.

Figures 4e and 4f are cross-sectional views taken along lines B-B' and C-C' in Figure 3, and correspond to the gate wiring extraction portion and the intersection of the gate metal wiring 4' and the source wiring 11, respectively. .

Effects of the Invention As is clear from FIG. Since the gate metal wiring layer 4' is configured to pass under the gate metal wiring layer 4' via the insulating layer 3', the effective step difference at the intersection of the multilayer wiring is reduced.
As a result, there are no step breaks at the intersections of the multilayer wiring. Furthermore, the dielectric strength between the multilayer interconnects has been significantly improved due to the dual structure of an insulating layer, an amorphous silicon layer, and an insulating layer.

Note that the present invention is applicable not only to amorphous silicon but also to silicon materials other than single crystal silicon, ie, microcrystalline silicon and polycrystalline silicon.

As described above, the present invention reduces the effective step difference at the intersection of multilayer wiring, prevents disconnection, significantly improves the dielectric strength, and is not limited by pulse operation, making it possible to display images or drive them. A semiconductor device suitable for circuits and the like can be obtained. Furthermore, compared to the conventional example, the number of photomask processes is increased by only one, and the impact on manufacturing costs is small.

[Brief explanation of drawings]

FIG. 1 is a schematic plan view of an MIS transistor with a conventional configuration, FIGS. 2 a to d are cross-sectional views of the manufacturing process along line A-A' of the transistor in FIG.
f is a sectional view on line B-B', C-C' in Figure 1,
4 is a schematic plan view of an MIS type transistor according to an embodiment of the present invention, FIGS. 4a to 4d are sectional views of the manufacturing process of the transistor shown in FIG.
f is a cross-sectional view of the transistor shown in FIG. 3 taken along lines B-B' and C-C'. 1... Insulating substrate, 2, 2'... First non-single crystal semiconductor layer, 3, 3'... First insulating layer, 4,
4'... Gate metal layer, 6, 6'... Second non-single crystal semiconductor layer, 8... Second insulating layer, 11, 12...
...Source/drain wiring, 13... Gate lead-out wiring, 14, 15... Source/drain, 16...
Third insulating layer, 17, 18... source/drain connection wiring.

Claims (1)

[Claims] 1. A first metal layer serving as source/drain wiring is formed on an insulating substrate, and an island-shaped metal layer mainly composed of silicon is formed on the insulating substrate via the first insulating layer. a first non-single crystal semiconductor layer is formed;
A laminated portion consisting of a second insulating layer and a second metal layer serving as a gate electrode is formed on a part of the non-single-crystal semiconductor layer of the second non-single-crystal semiconductor layer. A second non-single-crystal semiconductor layer deposited on a region other than the insulating layer and containing silicon as a main component and containing impurities serving as a donor or acceptor serves as a source/drain, and includes the first metal layer and the source/drain. a third insulating layer having an opening is formed;
An insulated gate transistor characterized in that a third metal layer is formed that includes the opening and connects the first metal layer and the source/drain. 2. A step of selectively forming a first metal layer that will become a source/drain wiring layer on an insulating substrate, a first insulating layer on the entire surface, a first non-single crystal semiconductor layer mainly composed of silicon, a step of sequentially forming a second insulating layer, a second metal layer, the first metal layer and a second non-single crystal semiconductor layer containing impurities, and thin film layers using different etching agents; a step of selectively forming a laminated portion consisting of a second metal layer and a second insulating layer; and a step of forming a second non-single crystal semiconductor layer containing silicon as a main component and an impurity serving as a donor or acceptor on the entire surface. a step of forming the first non-single crystal semiconductor layer and the second non-single crystal semiconductor layer including the laminated portion in an island shape; and removing the thin film layer and removing the second non-single crystal semiconductor layer on the thin film layer. selectively removing the crystalline semiconductor layer; depositing a third insulating layer on the entire surface; and removing the third insulating layer on the second metal layer and the second non-single crystal semiconductor layer. said first including
forming an opening in the first and third insulating layers on the metal layer; and forming an opening in the second insulating layer through the opening.
and a third metal layer connecting the first metal layer and the second non-single crystal semiconductor layer within the opening, on the third insulating layer. 1. A method of manufacturing an insulated gate transistor, the method comprising: forming a transistor. 3. The insulated gate transistor according to claim 2, wherein after forming the first non-single crystal semiconductor layer, the second insulating layer is continuously formed without being exposed to the atmosphere. Production method.