JPH0441504B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit formed by integrating CMOS circuits.

[Technical background of the invention and its problems]

As CMOS integrated circuits become more highly integrated, voltage fluctuations in power supply lines are becoming a serious problem. This will be explained using FIGS. 1 and 2.

FIG. 1 shows a schematic configuration of a CMOS type integrated circuit. 1 is a semiconductor chip with an integrated CMOS circuit, 2 is a VDD line, and 3 is a GND line. For example, output buffers 4 are arranged around the chip. The VDD line 2 and GND line 3 are connected to a VDD terminal 7 and a GND terminal 8 outside the chip by wire bonding via bonding pads 5 and 6, respectively.

In such a CMOS type integrated circuit, VDD
When the loop of terminal 7 - output buffer 4 - GND terminal 8 is shown as an equivalent circuit, inductances 9 ₁ and 9 ₂ and resistors 10 ₁ and 10 ₂ are included as shown in FIG.
These inductances 9 ₁ , 9 ₂ and resistance 10
₁ , 10 ₂ are VDD line 2 and GND line 3
They exist in wires, bonding wires, and other objects, and the smaller the device becomes due to higher integration, the relatively larger its influence becomes. For example, when the output buffer 4 switches, a voltage fluctuation of Ldi/dt occurs on the VDD line 2 and the GND line 3 due to the charging/discharging current at that time. this is
This causes unstable operation of the CMOS circuit and, in turn, induces a latch-up phenomenon due to conduction of the parasitic bipolar transistor.

Conventionally, efforts have been made to suppress such voltage fluctuations in power supply lines. Figure 3 is an example. The difference from Figure 1 is that there are four
VDD terminals 7 ₁ to 7 ₄ and GND terminals 8 ₁ to 8 ₄ are prepared, and the power lines are connected in parallel. As a result, the parasitic inductances 9 ₁ and 9 ₂ and the parasitic resistances 10 1 and 10 ₁ shown in FIG.
10 ₂ can be made smaller.

However, this method has the disadvantage that among the plurality of terminals on the package, only a few terminals can be used as signal terminals other than power supply terminals.

[Purpose of the invention]

The present invention has been made in view of the above points, and is designed to effectively suppress voltage fluctuations in the power supply line.
The purpose is to provide CMOS type semiconductor integrated circuits.

[Summary of the invention]

In the present invention, a power line stabilizing circuit using bipolar transistors is fabricated separately from the CMOS circuit on a semiconductor substrate on which the CMOS circuit is integrated. That is, in a structure in which a CMOS circuit is integrated by forming a second conductivity type well on a first conductivity type semiconductor substrate, the second conductivity type well provided separately from the CMOS circuit is used as a base, and a first conductivity type layer is formed within this base. A bipolar transistor is constructed with the substrate as the collector. This transistor is interposed between the first power supply line and the power supply terminal to which it is to be connected. Further, a resistor element is interposed between the collector and base of the transistor. and the second, which becomes the base of the transistor.
A capacitor is constructed by using the conductive well as one electrode and providing a counter electrode thereon via an insulating film, and the counter electrode is connected to a second electrode line to construct a power line stabilization circuit.

Here, if the CMOS circuit has a P-well structure, the bipolar transistor is NPN and
The first power supply line is a positive power supply (VDD) line, the second power supply line is a ground (GND) line,
In the N-well structure, the bipolar transistor
It is a PNP, and the first power supply line is a ground (GND) line, and the second power supply line is a positive power supply (VDD) line.

〔Effect of the invention〕

According to the present invention, voltage fluctuations in a power supply line can be effectively suppressed by a stabilizing circuit using a bipolar transistor integrated in a pair with a CMOS circuit. Furthermore, since there is no need to increase the number of power supply terminals, there is no restriction on the number of signal terminals other than power supply terminals. Another great advantage is that the stabilizing circuit, which consists of bipolar transistors, resistive elements, and capacitors, can be created without changing the manufacturing process of conventional CMOS integrated circuits.

[Embodiments of the invention]

Examples of the present invention will be described below. FIGS. 4 and 5 are an equivalent circuit and a cross-sectional structure showing the main parts of an embodiment in which the present invention is applied to a CMOS type integrated circuit having a P-well structure. A P-well 12 is formed using an N-type Si substrate 11 by a well-known process, and a CMOS
Integrate and form circuits. In the figure, only one output buffer 13 is shown. 14 and 15 are the VDD line and GND line of the CMOS circuit, respectively, and 16 is the output terminal of the output buffer 13. On the other hand, in addition to the P well 12 constituting the CMOS circuit, a P well 17 formed at the same time is provided on the Si substrate 11. Using this P well 17 as a base, an N ⁺ emitter layer 18 is formed within the P well 17. An NPN bipolar transistor 19 is constructed using the substrate 11 as a collector. This transistor 19 is interposed between the VDD line 14 and the VDD terminal 20 to which it is to be connected. i.e. VDD
Line 14 is N ⁺ emitter layer 18-P well 17
(base) - connected to a VDD terminal 20 such as a bonding pad via an N-type substrate 11 (collector). GND line 15 is directly connected to GND terminal 21. On the other hand, the P-well 17, which is the base of the transistor 19, is used as one electrode, and a counter electrode 23 made of, for example, polycrystalline silicon is provided on the P-well 17, which is the base of the transistor 19, with an insulating film 22 interposed therebetween, thereby forming a capacitor 24.
This counter electrode 23 is connected to the GND line 15. Further, a resistor element 25 is interposed between the collector and base of the transistor 19. In this example, the resistance element 25 utilizes a polycrystalline silicon film formed on the substrate 11 with an insulating film 22 interposed therebetween.
That is, the resistance element 25 and the opposing electrode 2 of the capacitor
3 can be formed simultaneously in the process of forming a polycrystalline silicon gate electrode of a CMOS circuit. In this way, a power line stabilizing circuit 26 consisting of a transistor 19, a resistive element 25, and a capacitor 24 is provided between the VDD terminal 20 and the VDD line 14 as a pair with the CMOS circuit.

According to this embodiment, the influence of power supply voltage fluctuations is effectively suppressed. That is, the resistive element 25 and the capacitor 24 constitute a filter, remove high frequency noise from the external power supply, and provide a smoothed and stable DC potential to the base of the transistor 19. As a result, the emitter of the transistor 19, ie, the VDD line 14, is supplied with a DC voltage from which fluctuations in the external power supply voltage have been removed. Furthermore, if the VDD line 14 is to fluctuate due to switching of the output buffer 13 or the like, this is also compensated for. That is, when the voltage on the VDD line 14 decreases, the conductivity of the transistor 19 increases, and conversely, when the voltage on the VDD line 14 increases, the conductivity of the transistor 19 decreases, thereby suppressing voltage fluctuations on the VDD line 14. will be done. It is also possible to provide the power line stabilizing circuit 26 outside the chip, but parasitic inductances 9 ₁ and 9 ₂ and parasitic resistances 10 ₁ and 10 ₂ are inserted between the power lines 14 and 15 on the chip and the power line stabilizing circuit. It will be done. Therefore, fluctuations in the external power supply voltage can be eliminated, but on the other hand, power supply noise generated inside the chip is not immediately transmitted to the power line stabilization circuit, and therefore there is no power supply stabilizing effect. That is,
It is important to build a power line stabilization circuit on-chip.

Further, in this embodiment, the stabilizing circuit 26 is
When integrated with CMOS circuit, normal
There is no need to change the CMOS circuit manufacturing process at all, and there is no need to increase the number of terminals as in the example illustrated in FIG.

In the above embodiment, a polycrystalline silicon film is used as the resistor element 25, but the resistor element 25 can be replaced with a MOS transistor 27 as shown in FIG. In this case, since the MOS transistor 27 is a P channel, its gate is
By connecting to the Vss line 23, it functions as a resistance element.

This embodiment also provides the same effects as the previous embodiment. Especially when high resistance is required,
This is advantageous because it can be realized with a smaller occupied area than when using a polycrystalline silicon film as shown in FIG.

In addition, the reason why bipolar transistors are used in the examples is that, compared to MOSFETs, firstly, the internal resistance is lower and there is less voltage drop even when a large current flows, and secondly, the voltage drop between base and emitter (VBE) is more constant-voltage (i.e., VBE is an exponential function of IB for bipolar devices, whereas for MOSFETs the gate-source voltage (VGS)
is proportional to the square of the gate voltage). For these reasons, bipolar transistors are suitable for use in power supply stabilization circuits.

Although the above embodiment is an example applied to a P-well type CMOS integrated circuit, the present invention can also be applied to an N-well type CMOS integrated circuit.
The embodiment is shown in FIG. 7, FIG. 8, and FIG. 9 corresponding to FIG. 4, FIG. 5, and FIG. 6 of the previous embodiment, respectively. Portions corresponding to those in the previous embodiment are designated by the same numbers with a suffix a, and detailed description thereof will be omitted. In this embodiment, the bipolar transistor 19a is PNP, so
In contrast to the previous example, this is connected to the GND line 15.
It will be interposed between the terminal a and the GND terminal 21a.

It is clear that this embodiment also provides the same effects as the previous embodiment.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the schematic configuration of a conventional CMOS integrated circuit, Figure 2 is an equivalent circuit diagram to explain the influence of power supply voltage fluctuations, and Figure 3 is a conventional CMOS integrated circuit that suppresses power supply voltage fluctuations. 4 is an equivalent circuit diagram showing the main structure of a CMOS integrated circuit according to an embodiment of the present invention, FIG. 5 is a cross-sectional view of the same, and FIG. 6 is a CMOS integrated circuit of another embodiment. The cross-sectional views of FIGS. 7 to 9 showing the configuration of essential parts of the circuit correspond to FIGS. 4 to 6 of other embodiments, respectively. 11, 11a... Si substrate, 12, 12a... Well (for CMOS circuit), 13, 13a... Output buffer, 14, 14a... VDD line, 15,
15a...GND line, 16, 16a...output terminal, 17, 17a...well (base), 18,
18a... Emitter, 19, 19a... Bipolar transistor, 20, 20a... VDD terminal,
21, 21a...GND terminal, 22, 22a...
Insulating film, 23, 23a... Counter electrode, 24, 24
a... Capacitor, 25, 25a... Resistance element (polycrystalline silicon), 26, 26a... Power line stabilization circuit, 27, 27a... MOS transistor (resistance element).

Claims (1)

[Scope of Claims] 1. In a semiconductor integrated circuit in which a CMOS circuit is integrated by forming a second conductivity type well in a first conductivity type semiconductor substrate, a second conductivity type well formed in the semiconductor substrate separately from the CMOS circuit is provided. A bipolar conductive type wire, which is interposed between a first power supply line and a power supply terminal to which it is to be connected, has a conductivity type well as a base, a first conductivity type layer formed in the base as an emitter, and the semiconductor substrate as a collector. A transistor, a resistance element interposed between the base and collector of the transistor, and a second conductivity type well serving as the base of the transistor as one electrode, and a counter electrode provided thereon via an insulating film. A semiconductor integrated circuit comprising a power line stabilizing circuit including a capacitor having a counter electrode connected to a second power line. 2. The semiconductor integrated circuit according to claim 1, wherein the first conductive type semiconductor substrate is an N-type substrate, the first power supply line is a positive power supply line, and the second power supply line is a ground line. 3. The semiconductor integrated circuit according to claim 1, wherein the first conductivity type semiconductor substrate is a P-type substrate, the first power supply line is a ground line, and the second power supply line is a positive power supply line. 4. The semiconductor integrated circuit according to claim 1, wherein the resistance element is a polycrystalline silicon film formed on the semiconductor substrate with an insulating film interposed therebetween. 5. The semiconductor integrated circuit according to claim 1, wherein the resistance element is a MOS transistor formed on the semiconductor substrate.