JPH0441632Y2 - - Google Patents

Description

[Detailed explanation of the invention] [Industrial application field] The invention uses two MOS FETs (Metal Oxide
This paper relates to improving the characteristics of a switch circuit constructed by connecting semiconductors in series.

[Prior Art] Conventionally, as this type of switch circuit, for example,
The one shown in Figure 7 was found.

In the figure, Q1 and Q2 are MOS FETs whose sources are connected. Also,
An input is given to the drain of Q1, and an output is taken out from the drain of Q2.

1 is the first terminal, MOS FETQ1 and Q2
gate is connected.

2 is the second terminal, MOS FETQ1 and Q2
source is connected.

The control voltage V _C applied between these first and second terminals 1 and 2 causes the MOS FETs Q1 and Q2 to
turns on and off.

R ₁ is a shunt resistor, and both ends thereof are connected to the first and second terminals 1 and 2. The shunt resistor _R1 is provided to turn off the MOS FETs Q1 and Q2 when the impedance between the terminals 1 and 2 becomes high.

Now, when the control voltage V _C is off (low level) and the input is a positive voltage, the circuit in FIG. 7 can be equivalently regarded as the circuit in FIG. 8. In FIG. 8, the same parts as in FIG. 7 are given the same reference numerals. The same applies to the figures below.

In FIG. 8, C _DG and C _GS are parasitic capacitors between the gate and drain and between the gate and source of the MOS FETQ. D2 is a parasitic diode of MOS FETQ2. Ignoring this voltage drop across diode D2, the circuit of FIG. 8 can be equivalently regarded as the circuit of FIG. 9. When a step voltage V _D with a sufficiently fast rise and a height of V _i is applied to the drain of the MOS FETQ in the circuit shown in Fig. 9, the response of the gate voltage V _G is expressed as the following equation using the Laplace transform equation. .

V _G (s)=Z(s)/1/SC _RG +Z(s)・V _D ′(s
) Z(s)=R ₁ /SC _GS /1/SC _GS +R ₁ =R ₁ /SC _GS R ₁ +1
V _D (s) = V _i /S s: Laplace operator Z (s): Combined impedance of capacitor C _GS and resistor R ₁ Substituting the formula and formula into the formula, V _G (s) is as follows. Become.

V _G (s)=R ₁ /SC _GS R ₁ +1/1/SC _RG +R ₁ /SC _GS R ₁
+1・V _i /S=C _DG /C _GS +C _DG・1/S+1/(C _GS +C _R
G ) R ₁・V When _{the i} expression is inversely transformed by Laplace, V _G (t) becomes (t
is the time) as follows.

V _G (t)=C _DG /C _GS +C _DG・V _i・exp{−t/(C _GS +C _DG )R ₁ } [Problem to be solved by the invention] From these calculation results, the step voltage A time chart showing changes in V _D and gate potential V _G is shown in FIG. In Figure 10b, V _p
is the gate potential V _G immediately after the step voltage V _D rises, and V _p = _Vi・{C _DG /C _DG +C _GS }
become. Here, for example, C _DG = 0.1 pF, C _GS =
25pF, R ₁ = 1MΩ, V _i = 1000V, then V _G (0)
= 4V, and if the FET threshold V _T is less than 4V, the MOS FETQ is turned on and C _GS ×
It remains on for a certain amount of time T _ON on the order of R ₁ = 25 μsec. Therefore, there was a problem that the MOS FET could be destroyed.

The present invention has been made to solve the above-mentioned problems, and aims to realize a switch circuit that can prevent elements from burning out when a surge pulse with a fast rise is input.

[Means for solving the problem] The present invention is a switch circuit configured by connecting two MOS FETs _{Q 1} and Q ₂ in series, in which the gates of the two MOS FETs _{Q 1} and Q ₂ are connected. Two resistors R 2 and R ₃ connected in series between the first terminal 1 and the sources of the two MOS FETs Q ₁ and Q ₂ , and a connection between these two resistors R ₂ and R _{3 .} a shunt resistor _R1 and a capacitor _C1 , both ends of which are connected between the first and second terminals 1 and 2, respectively, and the two MOS Apply input (IN) to one of the drains of FETQ ₁ and Q ₂ ,
This switch circuit is characterized in that an output (OUT) is taken out from the other drain, and a control voltage V _C for on/off control is applied between the first and second terminals 1 and 2.

[Example] The present invention will be explained below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a switch circuit according to the present invention. Components in FIG. 1 that are the same as those in FIG. 7 are given the same reference numerals.

In Figure 1, R ₂ and R ₃ are resistors, and MOS
It is connected in series between the source of FETQ1 and the source of MOS FETQ2. The second terminal is connected to the resistor R ₂
Connected to connection point a of _R3 .

_C1 is a capacitor connected between the first and second terminals.

Next, the operation of such a switch circuit will be explained.

When the output end of the circuit shown in FIG. 1 is shorted and a positive voltage is input, the circuit equivalently becomes a circuit as shown in FIG. 2. In Figure 2, C _DS is MOS
It is a parasitic capacitor between the drain and source of the FET. For simplicity, consider the circuit shown in Figure 3 by ignoring the voltage drop across R ₃ and D ₂ and the current flowing through C _GS , MOS FET, and R ₁ .

FIG. 4 shows a time chart for explaining the operation when a step voltage is applied to the circuit of FIG. 3.
In FIG. 4, a to d are input voltages V _D and b, respectively.
This is a time chart showing changes in the potential V _S at a point, the potential V _G at a point c, and the potential difference V _GS between b and c.

Step voltage of height V _i as shown in Figure 4a
When V _D is input, the potential at point b decreases to 0 from time t ₁ (when the step voltage rises) with a time constant C _DS ·R ₂ as shown in b. Potential C _G is the time
From t ₁ , V _i is divided by capacitance, V _i・C _DG / (C _DS +
_C1 ). Therefore, V _GS = V _G - V _S once becomes negative as shown in Figure 4d, and then becomes with a time constant of C _DS・R ₂ .
The value approaches V _i・C _DG / (C _DS + C ₁ ). This value
When the MOS FET threshold is exceeded, the MOS FET
turns on and current I _D flows.

When the current I _D flows, the circuit in Figure 3 becomes the same as when the resistor shown by the dashed line is connected, and the resistor
Current I _D flows through R ₂ . A time chart showing the operation at this time is shown in FIG. At this time, the potential
Since V _S becomes resistance R ₂ and is lifted by I _D · R ₂ , after time t ₁ I _D · R ₂ with the time constant of C _DS · R ₂
approach. Therefore, V _GS in this case becomes smaller than V _GS in FIG. 4d by I _D ·R ₂ , and the current flowing through the MOS FET is limited. A circuit including C _GS and R ₁ has a similar size relationship.

[Effect] According to the circuit according to the present invention, the current flowing through the MOS FET is limited as shown in FIG.
Even if the MOS FET is turned on when a rapidly rising pulse such as a surge is input, it will not be destroyed.

In addition, since V _GS rises with the time constant of C _DS · R ₂ , there is a delay time from when the pulse is input until the MOS FET turns on, causing ringing at the rising part as shown in Figure 6. This is particularly effective for inputting surge waveforms.

[Brief explanation of the drawing]

Figure 1 is a block diagram of an embodiment of the switch circuit according to the present invention, Figures 2 and 3 are equivalent circuit diagrams of the circuit in Figure 1, and Figures 4 and 5 are explanations of the operation of the circuit in Figure 1. Figure 6 is a diagram showing an example of an input waveform, Figure 7 is a configuration diagram of a conventional example of a switch circuit, Figure 8 is an equivalent circuit diagram of the circuit shown in Figure 7, and Figure 9 is a diagram showing an example of an input waveform. Figure 10 is the equivalent circuit diagram of the circuit shown in Figure 9.
This is a time chart for explaining the operation of the circuit shown in the figure. Q1, Q2...MOS FET, _R1 ...Shunt resistance, _R2 , _R3 ...Resistor, _C1 ...Capacitor, 1
...first terminal, 2...second terminal.

Claims (1)

[Claims for Utility Model Registration] In a switch circuit configured by connecting two MOS FETs _{Q 1} and Q ₂ in series, a first terminal 1 to which the gates of the two MOS FETs _{Q 1} and Q ₂ are connected; and two resistors R ₂ and R ₃ connected in series between the sources of the two MOS FETs _{Q 1} and Q ₂ , and a connection point between these two resistors R ₂ and R ₃ . a shunt resistor R ₁ and a capacitor C 1 , both ends of which are connected between the second terminal 2 and the first and second terminals 1 and ₂ , respectively, and the two MOS FETs Q ₁ and Q ₂ Apply input (IN) to one of the drains of
A switch circuit characterized in that an output (OUT) is taken out from the other drain, and a control voltage V _C for on/off control is applied between the first and second terminals 1 and 2.