JPH0441672U

JPH0441672U -

Info

Publication number: JPH0441672U
Application number: JP8300890U
Authority: JP
Priority date: 1990-08-04
Filing date: 1990-08-04
Publication date: 1992-04-08

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例による半導体集積
回路装置を示す回路図、第２図はこの考案の一実
施例による試験判定回路内の回路図、第３図およ
び第４図はこの考案の他の実施例を示す試験判定
回路内の回路図、第５図は従来の半導体集積回路
装置の回路図である。１は外部入力ピン、２は外部出力ピン、３はス
キヤン入力ピン、４はスキヤン出力ピン、５はフ
リツプフロツプ、６は組合せ回路、７はスキヤン
回路、８は診断結果出力ピン、９は選択回路、１
０は回路ブロツク、１１はバス制御回路、１２は
試験判定回路、１３は第１の回路ブロツクの出力
、１４は回路ブロツク（第１を除く）の出力、１
５は一致回路、１６はＮＡＮＤ回路、１７はテス
ト周期カウントクロツク、１８はテスト周期カウ
ンタ、１８はイネーブル付フリツプフロツプ、２
０はエンコーダ、２１はＲＡＭアドレスカウンタ
、２２はフリツプフロツプ、２３はＯＲ回路、２
４はＮＯＲ回路、２５はＲＡＭ、２６はパラレル
ーシリアル変換回路、２７は診断モード入力、２
８は診断結果読み出しクロツク。なお、図中、同
一符号は同一、又は相当部分を示す。 FIG. 1 is a circuit diagram showing a semiconductor integrated circuit device according to an embodiment of this invention, FIG. 2 is a circuit diagram of a test determination circuit according to an embodiment of this invention, and FIGS. 3 and 4 are diagrams showing a semiconductor integrated circuit device according to an embodiment of this invention. FIG. 5 is a circuit diagram of a test determination circuit showing another embodiment, and is a circuit diagram of a conventional semiconductor integrated circuit device. 1 is an external input pin, 2 is an external output pin, 3 is a scan input pin, 4 is a scan output pin, 5 is a flip-flop, 6 is a combinational circuit, 7 is a scan circuit, 8 is a diagnostic result output pin, 9 is a selection circuit, 1
0 is the circuit block, 11 is the bus control circuit, 12 is the test judgment circuit, 13 is the output of the first circuit block, 14 is the output of the circuit block (excluding the first), 1
5 is a coincidence circuit, 16 is a NAND circuit, 17 is a test period count clock, 18 is a test period counter, 18 is a flip-flop with enable, 2
0 is an encoder, 21 is a RAM address counter, 22 is a flip-flop, 23 is an OR circuit, 2
4 is a NOR circuit, 25 is a RAM, 26 is a parallel to serial conversion circuit, 27 is a diagnostic mode input, 2
8 is a diagnostic result reading clock. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims

[Scope of utility model registration request]

In a semiconductor integrated circuit device having a configuration in which a plurality of basic circuit blocks are arranged side by side, there is a selection circuit in which a signal applied to the first circuit block is also applied to all other circuit blocks, and a selection circuit that applies the signal applied to the first circuit block. A semiconductor integrated circuit device comprising a test determination circuit that determines whether an output signal and output signals of other circuit blocks are all the same and generates an error signal if they are different.