JPH0441850B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a semiconductor device called a coincidence element, which outputs the input logic level only when multiple inputs are inputted and the multiple inputs match, and the device is used for propagating the transfer control pulse. This relates to an asynchronous self-propelled data transmission path. [Prior Art] Generally, a coincidence element (hereinafter referred to as a C element) is a logic circuit that outputs C in response to two inputs X and Y, and operates according to the logic value table shown below. That is, when the two inputs X and Y match, the coincidence output C becomes the same level as the input level, and when the two inputs X and Y are different, the previous state is held (HOLD).

[Problem that the invention seeks to solve]

However, since the output of the C element depends only on stray capacitance, this C element has a problem that it is susceptible to noise and the output level deteriorates over time. In addition, in a data transmission path using the above-mentioned C element in the transfer control circuit, if the transfer control pulse changes due to noise when data is stored in parallel data buffers in multiple stages, the data for one stage may be lost. There were also problems in that the power consumption was high due to transient current. The first invention of the present invention was made to eliminate the drawbacks of the conventional devices as described above, and provides a semiconductor device that has high noise resistance, can eliminate transient current, and has a high pulse propagation speed. The purpose is to obtain. A second aspect of the present invention is to provide a data transmission path in which the transfer control circuit has high noise resistance and can transmit data at high speed without losing data in the data buffer. [Means for Solving the Problems] The semiconductor device according to the first invention of the present application includes a second CMOS inverter for inverting the coincidence output of the first CMOS inverter at the latter stage of the series connection body and feeding it back to the intermediate output.
A CMOS inverter is installed, and the latch circuit activates the second circuit only when the inputs of the device do not match.
It is made to function as a CMOS inverter. Further, the data transmission line according to the second invention of the present application uses the matching element configured as described above as its transfer control circuit. [Operation] In the first aspect of the present invention, the second CMOS inverter feeds back the output of the first CMOS inverter only when the inputs of the device do not match.
Only when the inputs of the device are different, the two CMOS inverters function as a latch, and the match output becomes a complete 0 or 1 level, and when the inputs of the device match, the feedback of the latch is cut off, so the series connection output is Collision between the outputs of the second inverter and the second inverter output is avoided. Further, in the second aspect of the present invention, since the matching element configured as described above is used as a transfer control circuit, the transfer control circuit has high noise resistance performance and data can be transferred without loss. Ru. Also, no transient current flows to the CMOS inverter,
Furthermore, since the transfer control pulse is propagated at high speed, data is transmitted at high speed. [Example] Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 shows a semiconductor device according to an embodiment of the first invention of the present application, and in the figure, the same reference numerals as in FIG. 6 indicate the same parts. 417 is P channel
A second CMOS composed of a MOS transistor 418 and an N-channel MOS transistor 419
an inverter, and the first CMOS inverter 4
This is for inverting the No. 14 output and feeding it back to node F (intermediate output). Also, 450 is 2 of this C element.
Only when the inputs X and Y do not match, the first and second
A latch circuit operation circuit that configures a latch circuit by CMOS inverters 414 and 417,
In the circuit 450, 451 and 453 are N-channel MOS transistors, and 452 and 454 are P-channel MOS transistors. Next, the operation will be explained. The basic operation of this embodiment is the same as that of the conventional one. However, in this embodiment, the latch circuit operation circuit 450 turns on the transistors 451 and 4 only when the two inputs X and Y do not match.
52 or transistors 453, 45
Since only one of the paths by 4 is turned on and the output of the second CMOS inverter 417 is transmitted to node F, a latch structure is formed by the CMOS inverters 414 and 417, so the C output cannot be a complete 1 or 0. It can be output.
That is, the two inputs X and Y of the device are 0, 1 or 1,
0, the node F is in a floating state, but in this embodiment, only in such a case, one of the paths in the latch circuit operation circuit 450 is turned on, and the output of the second CMOS inverter 417 becomes the node F.
Therefore, when the C output is relatively close to 1 (or 0), the output of the second CMOS inverter 417 is relatively close to 0 (or 1), and thereafter, due to the feedback described above, the intermediate The output and therefore the match output is completely 1 (or 0)
Since the CMOS inverter is resistant to noise, no transient current flows through the CMOS inverter, and the output level does not deteriorate. Also, when the two inputs X and Y of the C element match, the MOS transistor 4 of the latch circuit operating circuit 450
Since both the path through MOS transistors 51 and 452 and the path through MOS transistors 453 and 454 are cut off, the output of the series connection body 400 and the second path are cut off.
There is no collision with the output of the CMOS inverter 417, and it is possible to prevent propagation delay from occurring due to the collision. In this way, in this embodiment, only when the two inputs X and Y of the matching element do not match, the second CMOS inverter inverts the matching output of the first CMOS inverter and feeds it back to the intermediate output of the series connected body. Therefore, it is much more resistant to noise than conventional devices that hold the output only by stray capacitance, can output a complete 1 or 0 level, and when the two inputs of the C element match, the second Since the feedback of the matching output by the CMOS inverter is stopped, the output of the series connection body and the output of the second CMOS inverter will not collide, and the occurrence of propagation delay due to this can be prevented. FIG. 2 shows a data transmission path according to an embodiment of the second invention of the present application, and in the figure, the same reference numerals as in FIG. 1 indicate the same parts. 420a-420c
are 1-bit latches 40 constituting a parallel data buffer (data storage means) 311, respectively.
5 to 407 are n-channel MOS transistors, 4
08-413 are inverters. Next, the effects will be explained. In this embodiment, since the matching element configured as described above is used as a transfer control circuit, it is resistant to noise and data in the data latch can be transmitted without being lost. Furthermore, since no transient current flows through the CMOS inverter of the matching element, it is possible to further reduce power consumption. Moreover, since the feedback of the latch is stopped while the node F of the matching element is driving the next stage, collision between the outputs of the series connection unit and the first CMOS inverter is avoided, and the propagation speed of the transfer control pulse is increased. Is possible. Although the embodiments shown in FIGS. 1 and 2 show a C element with two inputs, a C element with three or more inputs can also be easily constructed, and exhibits the same efficiency as the above embodiment. Further, in the embodiment shown in FIG. 2, each latch is constructed using two inverters and one MOS transistor, but a double-channel transfer gate may be used instead of the MOS transistor, and the same effect as in the above embodiment can be obtained. play. In the embodiment shown in FIG. 2, the parallel data buffer is a dynamic latch in which data is held only by the stray capacitor CS, but an edge trigger type latch 430 as shown in FIG.
Alternatively, a transparent latch 440 as shown in FIG. 4 may be used, which provides the same efficiency as the above embodiment. In addition, in Figure 3, 42
5 to 429 are inverters, and 421 to 424 are n-channel MOS transistors, and both-channel transfer gates may be used instead of the MOS transistors. Also, 445,446 in Figure 4
is an inverter, 435, 436 are both channel transfer gates, 431, 433 and 43
2 and 434 are P and N channel MOS transistors forming both channel transfer gates 435 and 436, respectively. [Effects of the Invention] As described above, according to the semiconductor device according to the first aspect of the present invention, only when the inputs of the device do not match, the matching output is inverted by the second CMOS inverter, and the matching output is inverted between the series-connected bodies. Since it is fed back to the output, the intermediate output of the matching element is latched and the intermediate output becomes completely 0 or 1, so that no transient current flows and the noise resistance performance is improved. Moreover, when the inputs of the device match, the feedback of the second CMOS inverter is stopped, so the series connection body and the second
This has the effect of avoiding output collision with the CMOS inverter and improving pulse propagation speed. Further, according to the data transmission line according to the second aspect of the present invention, since the semiconductor device configured as described above is used as its transfer control circuit, power consumption is low and data can be transferred at high speed without loss. There is an effect that can be achieved.

[Brief explanation of the drawing]

1 and 2 are diagrams showing a semiconductor device and a data transmission line according to an embodiment of the first and second inventions of the present application, and FIGS. 3 and 4 are diagrams showing a semiconductor device and a data transmission line according to another embodiment of the invention of FIG. FIG. 5 is a diagram showing a latch, FIG. 5 is a diagram showing a data transmission path, and FIG. 6 is a diagram showing a matching element already developed by the applicant. In the figure, 400 is a series connection body, 414, 4
17 is the first and second CMOS inverter, 450
are latch circuit operating circuits, 401, 402, 41
5,416,452,454 are P channel MOS
Transistor, 403, 404, 416, 41
9,451,453 are N-channel MOS transistors, 311-315 are parallel data buffers (data storage means), 420a-420c, 430,
440 is latch, 405-407, 421-42
4,432,434 are N-channel MOS transistors, 431,433 are P-channel MOS transistors, 408-413, 425-429, 44
5,446 is an inverter. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Scope of Claims] 1. A semiconductor device that receives multiple inputs and outputs the input level when the multiple inputs match, which is connected in series between a first power source and a second power source, and each of which has one of the multiple inputs. A series connection body of first and second conductivity type MOS transistors corresponding to the number of inputs, each of which is inputted, the lowest stage MOS transistor of the first conductivity type, and the top stage MOS transistor of the second conductivity type. a first CMOS inverter that inverts the intermediate output and outputs a coincidence output, which is the connection point between the second CMOS inverter and the intermediate output; a second CMOS inverter that inverts the coincidence output; and a latch circuit operation circuit that transmits the output of the second CMOS inverter to the intermediate output only when the multiple inputs do not match. 2. The latch circuit operation circuit includes a first conductivity type MOS transistor and a second conductivity type MOS transistor so that when the two input levels of the multi-input do not match, both ends of one of the series connected bodies become conductive. One parallel connection body formed by connecting both ends of two series connection bodies in which conductive type MOS transistors are connected in series, or a parallel connection body formed by connecting a plurality of parallel connection bodies in parallel, is used as the second CMOS. 2. The semiconductor device according to claim 1, wherein the semiconductor device is connected between an output of an inverter and the intermediate output. 3. In a data transmission path consisting of a shift register consisting of a plurality of data storage means and a transfer control circuit of each stage that controls the data storage means of its own stage in response to a control signal from a transfer control circuit of an adjacent stage, the above-mentioned transfer control circuit a series connection body of MOS transistors of first and second conductivity types, each having the number of inputs connected in series between a first power source and a second power source, each of which receives a plurality of inputs; a first CMOS inverter that inverts an intermediate output that is a connection point between the bottom-stage MOS transistor of the first conductivity type and the top-stage MOS transistor of the second conductivity type and outputs a coincidence output; and a first CMOS inverter that inverts the coincidence output. a second CMOS inverter provided between the output of the second CMOS inverter and the intermediate output, and operating a latch circuit that transmits the output of the second CMOS inverter to the intermediate output only when the multiple inputs do not match. A data transmission path characterized by using a matching element consisting of a circuit. 4. The latch circuit operating circuit includes a first conductivity type MOS transistor and a second conductivity type MOS transistor so that when the two input levels of the multi-input do not match, both ends of one of the series connected bodies become conductive. One parallel connection body formed by connecting both ends of two series connection bodies in which conductive type MOS transistors are connected in series, or a parallel connection body formed by connecting a plurality of parallel connection bodies in parallel, is used as the second CMOS. 4. The data transmission line according to claim 3, wherein the data transmission line is connected between an output of an inverter and the intermediate output.