JPH0410251B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a semiconductor device called a coincidence element that outputs the input logic level only when two inputs are input and the two inputs match, and the device is used for propagating the transfer control pulse. This relates to an asynchronous self-propelled data transmission path. [Prior Art] In general, a coincidence element (hereinafter referred to as a C element) is a C element for two inputs X and Y.
It is a logic circuit that outputs , and operates according to the logic value table shown below. That is, when the two inputs X and Y match, the coincidence output C has the same level as the input level, and when the two inputs X and Y are different, the previous state is held (HOLD).

[Problem that the invention seeks to solve]

However, since the output of the C element depends only on stray capacitance, this C element has a problem that it is susceptible to noise and the output level deteriorates over time. Furthermore, if the intermediate output becomes floating before the output of the series-connected C element becomes full swing, the intermediate output will be at an intermediate level between 1 and 0, and a transient current will flow to the CMOS inverter of the C element. There was also the problem of it flowing. In addition, in a data transmission line using the above-mentioned C element in the transfer control circuit, when data is stored in parallel data buffers in multiple stages, if the transfer control pulse changes due to noise, data for one stage will be lost. There was also the problem that the power consumption was large due to the transient current. The first invention of this invention was made in order to eliminate the drawbacks of the conventional ones as described above, and it is a CMOS inverter that has high noise resistance, high pulse propagation speed, and no transient current flows through the CMOS inverter. The purpose is to obtain equipment. A second aspect of the present invention is to obtain a data transmission path that can transmit data at high speed without losing data and can reduce power consumption. [Means for solving the problem] The semiconductor device according to the first invention of the present application has a first CMOS inverter for inverting the coincidence output of the first CMOS inverter at the latter stage of the series connection body and feeding it back to the intermediate output. 2 of
A CMOS inverter is provided, and the output of the second CMOS inverter is transmitted to the intermediate output only when the two inputs of the device are different, using an exclusive OR circuit and both channel transfer gates. Further, a data transmission line according to a second aspect of the present invention uses the matching element configured as described above as its transfer control circuit. [Operation] In the first aspect of the present invention, the output of the second CMOS inverter is transmitted to the intermediate output only when the two inputs of the device are different.
The inverter functions as a latch and the match output is completely at 0 or 1 level, and when the two inputs of the device match, the series connection output and the second
Since the connection with the CMOS inverter output is cut off, collision between the two outputs is avoided. In addition, in the second aspect of the present invention, since the matching element configured as described above is used as a transfer control circuit, the noise resistance performance is high, and no transient current flows to the CMOS inverter, so transfer control Pulses are propagated at high speed and without errors. [Example] Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 shows a semiconductor device according to an embodiment of the first invention of the present application, and in the figure, the same reference numerals as in FIG. 6 indicate the same parts. 417 is P channel
A second CMOS composed of a MOS transistor 418 and an N-channel MOS transistor 419
an inverter, and the first CMOS inverter 4
This is for inverting the No. 14 output and feeding it back to node F (intermediate output). 450 is the matching element 2
470 is a double-channel transfer gate provided between the output of the second CMOS inverter 417 and node F, and this is a P-channel MOS Transistor 471 and N channel MOS
It is composed of a transistor 472. Further, 460 is a third CMOS inverter that inverts the output of the exclusive OR circuit 450, which is connected to a P channel MOS transistor 461 and an N channel MOS inverter.
It is composed of a MOS transistor 462. Next, the operation will be explained. The basic operation of this embodiment is the same as that of the conventional one. However, in this embodiment, the exclusive OR circuit 450 and the third CMOS
The inverter 460 turns on both channel transfer gates 470 only when the two inputs X and Y do not match, and the first and second CMOS inverters 414,
Since the latch structure is formed by 417, a complete 1 or 0 can be output as the C output. That is, the two inputs X and Y of the device are 0, 1 or 1,
0, node F is in a floating state, but in this embodiment, both channel transfer gates 470 are turned on only at this time, and the output of the second CMOS inverter 417 is transmitted to node F, so that the C output becomes, for example, When the value is relatively close to 1 (or 0), the output of the second CMOS inverter 417 becomes a value relatively close to 0 (or 1), and thereafter the C output becomes completely at the 1 (or 0) level due to the feedback described above. Since the output level rises to , it is possible to obtain a product that is resistant to noise and has no deterioration in output level. Furthermore, since a double-channel transfer gate is used to transmit the output of the CMOS inverter 417 to the node F, the output of the inverter 417 can be transmitted to the node F without dropping below 1 (or rising above 0). As a result, node F does not reach an intermediate potential, and no transient current flows through CMOS inverter 414. Also, when the two inputs X and Y of the C element match, the inverting exclusive OR circuit 450 outputs 1 and 3.
Since the output of the CMOS inverter 460 becomes 0 and both channel transfer gates 470 are turned off, the output of the series connection body 400 and the output of the second CMOS inverter 417 do not collide, and the occurrence of propagation delay due to the collision is prevented. can. In this way, in this embodiment, the output of the second CMOS inverter is transmitted to the intermediate output of the series connection body only when the two inputs X and Y of the matching element do not match, so that the output depends only on the stray capacitance. It is much more resistant to noise than the conventional one, and since a double-channel transfer gate is used to transmit the output of the second CMOS inverter to node F, node F receives the output value of the second CMOS inverter itself. is transmitted, and no transient current flows to the first CMOS inverter. Furthermore, in this embodiment, when the two inputs of the C element match, the feedback to the node F is stopped, so there is no collision between the output of the series connection unit and the output of the second CMOS inverter, and the propagation speed is reduced. Never. FIG. 2 shows a data transmission path according to an embodiment of the second invention of the present application, and in the figure, the same reference numerals as in FIG. 1 indicate the same parts. 420a-420c
are 1-bit latches 40 constituting a parallel data buffer (data storage means) 311, respectively.
5 to 407 are n-channel MOS transistors,
408 to 413 are inverters. Next, the effects will be explained. In this example, since the matching element configured as described above is used as the transfer control circuit, it is resistant to noise and data can be transmitted at high speed without error, and in addition, no transient current flows through the first CMOS inverter of the transfer control circuit. Therefore, it is possible to further reduce power consumption. In the embodiment shown in FIG. 2, each latch is constructed using two inverters and one MOS transistor, but a double-channel transfer gate may be used instead of the MOS transistor, and the same effect as in the above embodiment can be obtained. play. In the embodiment shown in FIG. 2, the parallel data buffer is a dynamic latch in which data is held only by the stray capacitor CS, but an edge trigger type latch 430 as shown in FIG.
Alternatively, a transparent latch 440 as shown in FIG. 4 may be used, and the same effect as in the above embodiment can be obtained. In addition, in Figure 3, 4
25-429 are inverters, 421-424 are n
It is a channel MOS transistor, and a dual channel transfer gate may be used instead of the MOS transistor. Also, 445,446 in Figure 4
is an inverter, 435 and 436 are both channel transfer gates, and 431, 433 and 4 are inverters.
32 and 434 are P and N channel MOS transistors forming both channel transfer gates 435 and 436, respectively. [Effects of the Invention] As described above, according to the semiconductor device according to the first aspect of the present invention, only when two inputs of the device do not match, the inverted output value of the matching output can be connected in series without changing the value. Since the intermediate output of the matching element is latched, the intermediate output becomes completely 0 or 1, and the first CMOS
It is possible to prevent transient current from flowing into the inverter, improving noise resistance. Moreover, since the feedback of the second CMOS inverter is stopped when the inputs of the device match, collision of the outputs of the series connection body and the second CMOS inverter is avoided, which has the effect of improving the pulse propagation speed. Further, according to the data transmission line according to the second aspect of the present invention, since the semiconductor device configured as described above is used as its transfer control circuit, the noise resistance performance is high and data can be transmitted at high speed without error. Moreover, there is an effect that a device with low power consumption can be obtained.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a semiconductor device according to an embodiment of the first aspect of the present invention, FIG. 2 is a diagram showing a data transmission path according to an embodiment of the second aspect of the present invention, and FIG.
4 and 4 show another embodiment of FIG. 2, FIG. 5 shows a data transmission path, and FIG. 6 shows a conventional semiconductor device. In the figure, 400 is a series connection body, 401, 4
02 is a P channel MOS transistor, 403,
404 is an N-channel MOS transistor, 414,
417, 460 are first, second and third CMOS inverters, 415, 418, 461 are P channels
MOS transistors, 416, 419, 462 are N-channel MOS transistors, 470 is a double-channel transfer gate, 471 is a P-channel
MOS transistors, 472 is an N-channel MOS transistor, 311-315 are parallel data buffers (data storage means), 420a-420c are latches, 408-413 are inverters, 405-4
07 is an N-channel MOS transistor, 430,
440 is a latch, 425 to 429 are inverters,
421 to 424 are N-channel MOS transistors;
435 and 436 are double channel transfer gates, 431 and 433 are P channel MOS transistors, 432 and 434 are N channel MOS transistors, and 445 and 446 are inverters.

Claims (1)

[Claims] 1. In a semiconductor device that receives two inputs and outputs the input level when the two inputs match, the semiconductor device is connected in series between a first power source and a second power source, and each of the two inputs has an input level. each two first inputs,
a series connection body of MOS transistors of a second conductivity type;
a first CMOS inverter that inverts an intermediate output, which is a connection point between the bottom-stage MOS transistor of the first conductivity type and the top-stage MOS transistor of the second conductivity type, and outputs a coincidence output; and a first CMOS inverter that inverts the coincidence output. a second CMOS inverter;
A double-channel transfer gate connected between the output of the CMOS inverter and the intermediate output, and a normal or inverted transfer gate that receives the two inputs and applies its normal or inverted exclusive OR output to one control input of the transfer gate. an exclusive OR circuit; and a third CMOS that inverts the output of the exclusive OR circuit and applies it to the other control input of the transfer gate.
A semiconductor device comprising an inverter. 2. In a data transmission path consisting of a shift register consisting of a plurality of data storage means and a transfer control circuit of each stage that controls the data storage means of its own stage in response to a control signal from a transfer control circuit of an adjacent stage, the above-mentioned transfer control circuit a series connection body of two MOS transistors of a first conductivity type and a second conductivity type connected in series between a first power supply and a second power supply and each of which receives two inputs; The lowest conductive type
MOS transistor and second conductivity type top stage MOS
a first CMOS inverter that inverts an intermediate output that is a connection point with the transistor and outputs a matching output;
a second CMOS inverter that inverts the coincidence output; a double-channel transfer gate connected between the output of the second CMOS inverter and the intermediate output; and a normal or inverted exclusive OR of the two inputs that receive the two inputs. a normal or inverted exclusive OR circuit that applies an output to one control input of the transfer gate; and a third CMOS that inverts the output of the exclusive OR circuit and applies it to the other control input of the transfer gate. A data transmission path characterized by using a matching element consisting of an inverter.