JPH04420Y2 - - Google Patents

Description

[Detailed Description of the Invention] (Technical Field of the Invention) The present invention provides a logic circuit that inputs a sense signal and a detection timing pulse from a sense circuit to determine an error, and detects a failure in the sense circuit. The present invention relates to a switch erroneous reading detection circuit which checks for malfunction of a reading circuit.

(Technical background of the invention and its problems) FIG. 1 is a diagram showing an example of a conventional switch reading circuit, in which a drive is driven by inputting read timing pulses T1 and T2 output from a read timing generation circuit 2A. Switch 1 with diode configuring the matrix switch by circuit 3A
1, 12, 21 and 22 are controlled by the drive line 31.
A and 32A. Drive circuit 3A
is driven at the timing of reading the read timing pulses T1 and T2, and the read timing pulse T
Drive line 31A or 32 when inputting 1 or T2
A is held at ground potential.
In addition, the read timing generation circuit 2A is connected to the common line of the matrix switch (drive lines 31A, 32
This is a circuit that prevents two or more of A) from being driven to ground potential at the same time, and is generally constituted by a CPU address decoding circuit which is a known technology. Switch 1 making up the matrix switch
1 to 12 are diodes connected in series with the contact switches SW11 to SW22, and the contact switches SW11 to SW22 are turned ON (closed state) or OFF (open state), respectively. When a certain switch is turned ON, the sense lines 41A and 42A connected to that switch output a LOW (low level output; hereinafter referred to as "L") signal, and the connected switch is turned OFF. In the state, the sense lines 41A and 42A output a HIGH (high level output; hereinafter referred to as "H") signal. "H" and "L" of sense lines 41A and 42A are read by a sense circuit 4 and sent to a CPU input circuit 1 as an interface for a CPU (central processing unit).

The sense circuit 4 is generally pulled up with a resistor and has a known circuit configuration (for example, "Computer Handbook" edited by the Information Processing Society of Japan published by Ohm Publishing, Kazuto Kenno and Inaba published by Taiga Publishing). ``Numerical Control Machine Tools'' by Seiemon).

Such a switch reading circuit has a drawback in that it is not possible to check for malfunctions in each circuit or switch when continuously reading signals on the sense lines 41A and 42A. In other words, when the power is turned on, the states of the sense circuit 4 and the switches 11 to 22 are read while they are not being operated, and it is only possible to check that they are OFF when they are not being operated.

(Purpose of the invention) The present invention was developed in view of the above-mentioned circumstances, and includes a logic circuit that inputs the sense signal and detection timing pulse from the sense circuit to determine an error, and detects a failure of the sense circuit. Therefore, it is an object of the present invention to provide a switch erroneous reading detection circuit that can check the switch reading circuit.

(Summary of the invention) The invention relates to a switch erroneous reading detection circuit, which includes a timing pulse generation circuit that cyclically outputs a read timing pulse and a detection timing pulse by address decoding of the CPU.
a drive circuit inputting the read timing pulse and having a drive line connected to an output part;
a sense circuit connected to a switch line and outputting a sense signal corresponding to the switch line; a diode matrix comprising a switch with a diode connected to each intersection of the drive line and the sense line; and a diode matrix for detecting the sense signal and the sense signal. a logic circuit that inputs a timing pulse, calculates a logical product of the negation of the sense signal and the detected timing pulse, and outputs an error signal; This is designed to detect failures.

(Embodiment of the invention) FIG. 2 is a diagram showing an embodiment of the invention in correspondence with FIG. 1. Timing pulse generation circuit 2
The read timing pulses T1 and T2 and the detection timing pulses are connected to drive lines 31B and 3, respectively.
2B drive circuit 3B and error detection
This is a circuit for cyclically generating pulses to the AND (logical product) circuit 6, and the read timing pulses T1, T2 and the detection timing pulse T3 are the third
As shown in Figures A to C, they are generated sequentially so as not to overlap. The drive circuit 3B drives the drive line 31A or 32B, respectively, when the read timing pulse T1 or T2 is sent.
1B connects switches 11 and 21 to drive line 32.
B turns on switches 12 and 22, respectively. Therefore, in both cases, the sense line 41B
and 42B both output "L" if they are ON, and "H" if they are OFF, depending on the state of the switch. When the detection timing pulse T3 is being sent, if all the circuits are operating normally, they will be in the OFF state.
Sense lines 41 and 42B output "H". However, if the sense circuit 4 remains in the ON state due to a failure or the like, the sense line (the sense line 42B in this example) will output "L".

In the present invention, the NAND (NOT AND AND) circuit 5 and
A logic circuit formed by connecting AND circuits 6 as shown is provided to detect the above-mentioned failure. That is, sense lines 41B and 42B
When the outputs of are used as sense signals S1 and S2,
The output of the NAND circuit 5 is S1+S2, and the output E1 of the AND circuit 6 which receives this output S1+S2 and the detection timing pulse T3 is expressed as E1=T3.(1+2)...(1). Therefore, when the detection timing pulse T3 is input to the AND circuit 6, if either of the sense lines 41B or 42B is "L" (a certain switch is in the ON state due to a failure), the equation (1) is satisfied. As a result, the error signal E1 is set to "H".
In this logic circuit, if all the output signal lines of the sense circuit 4 should be OFF, but even one signal line is ON, an error signal E1 is generated at the detection timing of the detection timing pulse T3.
The signal becomes "H", and a failure of the sense circuit 4 at times other than when the power is turned on can be detected.

FIGS. 3A to 3G are timing charts showing examples of the operation, and the read timing pulse T in FIG.
1, the sense signals S1 and S2 are turned ON or OFF depending on the states of the contact switches SW11 and SW21 (D and E in the same figure), and the output of the NAND circuit 5 is F in the same figure.
As shown in the figure, it becomes "H" or "L" depending on the states of the contact switches SW11 and SW21. Similarly, the contact switch is activated by the read timing pulse T2.
The sense signal S depends on the states of SW12 and SW22.
1 and S2 are turned ON or OFF, and the output of the NAND circuit 5 becomes "H" or "L" depending on the states of the contact switches SW12 and SW22. Drive circuit 3B
is driven at the read timing of the read timing pulses T1 and T2, and the drive line 3 is driven at the time of the read timing pulses T1 and T2.
1B or 32B is kept at ground potential L. As a result, as shown in FIG. 3D and E, the sense signal S1 or S2 is turned ON when the switch input is
Sometimes, when the "L" switch input is OFF, it is output as "H".

On the other hand, since the drive circuit 3B is not driven at the timing of the read timing pulse T3, the drive lines 31B and 32B are held at "H". Even if the detection timing pulse T3 shown in FIG. 3C is input at time t1, the output of the NAND circuit 5 remains "L", so the error signal E1 from the AND circuit 6 remains "L". It is.
However, at time t2, for example, the sense circuit 4
has failed, and the sense signal S
2 becomes "L", the output of NAND circuit 5 becomes "
At time t3 when the detection timing pulse T3 is input, the error signal E from the AND circuit 6 is
1 becomes "H". This makes it possible to detect a failure in the switch circuit. That is, at the read timing of the read timing pulses T1 and T2, the drive line 31B is activated by the drive circuit 3B.
and 32B are held at "L", the sense lines 41B and 42B are held at "L" due to the ON state of contact switches SW11 to SW22, and when the sense lines 41B and 42B are at "L", the contact switch is is ON and “H”, the contact switch is
Can be detected as OFF. On the other hand, since the drive circuit 3B is not driven at the detection timing of the detection timing pulse T3, both the drive lines 31B and 32B do not become "L".
holds sense signals S1 and S2 at "H".
However, if the sense signals S1 and S2 become "L" due to a circuit abnormality in a switch or a sense line, it can be detected as some kind of abnormality.

In addition, although positive logic was explained above, it goes without saying that negative logic may also be used.

(Effects of the invention) As described above, according to the invention, by checking the output of the sense line, an error detection signal is output even during circuit operation. This has the advantage of being able to check for defects.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of a conventional switch reading circuit, FIG. 2 is a circuit diagram showing an embodiment of this invention, and FIGS. 3A to 3G are timing charts showing examples of its operation. 1... CPU input circuit, 2... Timing pulse generation circuit, 3... Drive circuit, 4... Sense circuit, 5... NAND (NOT AND AND) circuit, 6...
AND (logical product) circuit, 11-22... switch,
31, 32... Drive line, 41, 42... Sense line.

Claims (1)

[Scope of utility model registration request] A timing pulse generation circuit that cyclically outputs a read timing pulse and a detection timing pulse by address decoding of the CPU, a drive circuit that inputs the read timing pulse and has a drive line connected to its output section, and a switch line. a sense circuit that is connected to the switch line and outputs a sense signal in response to the switch line; a diode matrix that includes a switch with a diode connected to each intersection of the drive line and the sense line;
a logic circuit that inputs the sense signal and the detection timing pulse, calculates a logical product of the negation of the sense signal and the detection timing pulse, and outputs an error signal; A switch erroneous reading detection circuit, characterized in that it detects a failure of the sense circuit.