JPH0442372A - Logic circuit editing system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Table of Contents Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Actions Examples Effects of the Invention [Summary] Logic circuits are manually edited into a database With regard to logic circuit editing methods registered in , an input editing means for inputting and editing a new logic circuit using an existing logic circuit expressed in a functional level format, and a database registration means for registering a target logic circuit obtained by input editing in a database. , has.

[Industrial Application Field] The present invention relates to a logic circuit editing method for inputting and editing a logic circuit and registering it in a database.

In CAD systems and DA systems that use electronic computers, input and editing of logic circuits is performed using a logic editor.
It will be compiled into a database.

[Prior Art] The conventional technology is explained in FIG. 11. When the creation of time charts, block diagrams, truth tables, and logical functional division are performed in advance for the logic circuit to be designed, Logical entry section 1100. 1102 to each logical symbol representation.

A target logic circuit is input using a batch language description expression.

These logic circuits are provided to the input editing section 1104. Editing results from the input editing section 11040 are output to the checking section 1106.

A check section 1106 performs an overall design rule check of the logic circuit to be designed, and the logic circuit after the card check is registered in a database by a database registration section 1108.

[Problems to be Solved by the Invention] Generally, logic circuits are newly designed using existing ones.

At that time, existing logic circuits are examined in advance at the functional level, and consideration is also given to changing some of the logic or making it compatible with other LSI technologies.

For this reason, in the past, a great deal of effort was spent on designing logic circuits, and it took a long time to develop them.The present invention has been made in view of the above-mentioned conventional circumstances.
The purpose is to provide a method that makes it possible to design logic circuits more efficiently.

[Means for Solving the Problems] In order to achieve the above object, the present invention adopts the method shown in FIG. 1.

In the figure, an existing logic circuit 10 is converted into a functional level expression format by an expression format conversion means 12.

Further, the input editing means 16 inputs and edits the new logic circuit 140. At that time, the existing logic circuit 10 expressed in the functional level format by the expression format converting means 12 is used.

The new logic circuit 14 obtained through this input editing is then registered in the database 18 by the database registration means 20.

[Operation] In the present invention, the existing logic circuit 10 (in whole or in part) is expressed at a functional level, so circuit examination can be performed at that level.

[Embodiments] Preferred embodiments of the system according to the present invention will be described below based on the drawings.

In Figure 2, Works Steel Silon 200°202.
204 and 206 are connected to the host computer 208, and a database of logic circuits prepared by the host computer 208 is used by the workstations 200, 202, and 206.

Work stage pins 200, 202゜204 for this system.
At step 206, a symbol expression, a batch type connection expression, a batch type function expression, and a truth value table expression are arbitrarily selected, and a new logic circuit is input and edited by using the existing circuit registered in the database.

This system is illustrated in FIG. 3, in which the existing logic circuit 10 searched in the database section 300 is provided to the conversion processing section 802.

The conversion processing unit 302 is provided with conversion units 304 and 308, and converts the existing logic circuit 1 obtained by database search.
0 is converted into a logical symbol expression (conversation type) and a batch type language description expression by the inverse conversion.

The existing logic circuit IO whose expression format has been converted by the conversion processing unit 302 is given to the data input unit 310 of the logic entry processing unit 308. .

Further, the operation input unit 812 of the logic entry processing unit 808 receives logic symbols and circuit design data expressed in batch language.

These data input sections 310. The data of the newly designed circuit inputted from the operation input section 312 is given to the editing section 314, and the edited result is outputted from the logic entry processing section 308 to the compression processing section 316.

In the compression processing section 316, partial circuits are cut out in function units based on the truth value contents. The compressed circuit data is given to the partial check processing section 318, where a simple self-check is performed.

Furthermore, the newly designed circuit data for which the partial circuit check has been completed is provided to the overall check processing section 320, where the overall design rule check is performed.

The newly designed circuit data for which the overall check has been completed by the overall check processing unit 320 is then transferred to the database creation unit 8.
22. This tag is registered in the database section 824 by the database creation section 822.

Further, the partial circuit compressed by the compression processing unit 816 and checked by the partial check processing unit 818 is converted into a library by the library creation unit 326. After the expression format is converted, this library data is sent to the library unit 328 from the conversion processing unit 302. will be registered.

FIG. 4 shows a newly designed logic circuit displayed on a graphic display, and when area 400 is designated, a window 450 is opened.

Then, the logical formula corresponding to the partial circuit in area 400 is displayed in window 450.

Furthermore, when the area 402 is specified, the window 452
The logical formula corresponding to the partial circuit in area 402 is displayed in window 452.

As a result, the logic of the circuit part in areas 400 and 402 can be confirmed at the functional level.

Also, by specifying the area 404, the line 4
54 is an open card. When the truth value table description is input from the data input section 310, a logical formula corresponding to the partial circuit displayed in the area 404 is displayed in the window 454.

In FIG. 5(A), the connections between the gates labeled with logic symbols 2AI, 2A2, and 4A within the area 400 are explained using a truth table, and in FIG. Similarly, connections between gates labeled with logic symbols 2A3, 2A4, and 2A5 are explained using a truth table.

When the logical expressions are displayed in the windows 450, 452, and 454 of FIG. 4, the processing of FIG. 7 is performed.

As shown in FIG. 8, an area 400 is specified and the area 400
9 is created using the back trace of the connection net within the extraction area 400 (step 700).

The backtrace at that time is KO → K 14 K 10 KO → K l-+ K21 KO → 2 → 20 KO → 2 → 21 KO → ni 2 → ni 22 KO → 2 → 23 LO→L1→LIO LO→Ll→Lll LO→L2→L20 LO→L2→L21 It is done as follows.

Next, the process of checking the logical connections within the cutout area 400 is performed as follows, and another work table shown in FIG. 10 is created (step 702).

KO (2A2) → Kl (2A 1) → KIOKO (
2A2) → Kl (2A I) → 21KO (2A2
) → 2 (4A) → 20KO (2A2) → 2 (4A)
) → 21 KO (2A2) → 2 (4A) → 22 KO
(2A2) → 2 (4A) → 23LO (2A5) → L
-1 (2A3) → LIDLO (2A5) → Ll (2A
3) →Ll+LO(2A5) →L2(2A4) →L
20LO (2A5) →L2 (2A4) →L21 When the logical connection relationship is confirmed in this way, the table in the library section 826 displays the logical identifier (AMD, OR;
FF, etc.) (step 704),
Its conclusion Each logical symbol 2A2.2AI, 4A, 2A
5.2A3.2A4 and their logical expressions are correlated as follows.

2A2: KO=to1・to2...Φth equation (1) 2A
1: K1=10・21---Equation (2) 4A:
K2=Ni20・K21@K22・Ni23 Shosha・Equation (3) 2A5: LO=L1+L2 ... Equation (4) 2A
3: L1=L10@Lll...Equation (5) 2A4:
L2=L20@L21...Equation (6) Then, the process of substituting each of the above logical expressions into the logical symbol part in the work table of FIG. 10 (step 70B), toward the final net on the input side. A process of converting logic while backtracing (step 708) is performed.

In other words, K=KO...In the case where the output of equation (7) is obtained, equations (2) and (3)
When the equation is substituted into equation (1), KO= (KIO-K
21) ” K2O-K21- K22- K2S)・
...Equation (8) is obtained.The output is K=(A-B)・(C-D-E-F)...The (9th)
) formula % formula % L=LO---In the case of formula (10), when formulas (5) and (6) are substituted into formula (4), LO=(LIO・Lll) + (L20+L21)・
...Equation (11) is obtained. The output is expressed by L=(GH)+(I+J)...Equation (12).

The above equation (9) and this equation (12) are associated with the display card area 400 in the window 450 as shown in FIG.

In this way, when the area 400 is specified, the window 450 is automatically opened and the logical formula of the area 400 is displayed in the window 450.

Therefore, inputs A, B, C, D, E, F
Designers can immediately confirm that an output K of 1 is obtained only when all are ``■'', and that the output K is 0 otherwise. can.

This can also be used as an effective support tool when creating a simulation pattern in the next simulation process and creating a test pattern.

Note that when the truth table system diagram shown in FIG. 5 is displayed, the truth table table in the library section 826 is referred to instead of the logical expression table.

Furthermore, when a circuit portion is manually designed, the data of the truth table description input through the data input section 310 is used.

When the logical conditions of the timing control circuit are expressed in a truth table as shown in FIG. 6(A) in the area 404 of FIG. The truth table (B) is created.

When the truth table shown in FIG. 4(C) is generated by the compression, the logical formula shown in FIG. 4(D) is displayed in the window 454 of FIG.

As explained above, according to this embodiment, the existing circuit portions are expressed at the functional level (logical expressions), so it is possible to design the circuit more efficiently.

Furthermore, since the input method of logic entries can be selected as appropriate depending on the purpose, logic design can be made more efficient.

Furthermore, when a part of the logic is changed (~), the circuit function can be confirmed from the logical formula of only the changed part, making the circuit change easy.

Since the circuit is checked on a functional basis, it is possible to improve the reliability of the circuit.

Furthermore, since it is easy to make partial changes to the circuit, it is possible to efficiently design large-scale integrated circuits by dividing them, and it is possible to efficiently transition between 0MO8 systems, gallium arsenide systems, etc. .

Further, since the circuit design process is performed in parallel and distributed manner as shown in FIG. 2, even extremely large-scale circuits can be efficiently designed in a short period of time.

[Effects of the Invention] As explained above, according to the present invention, the already designed circuit logic is expressed at the functional level, so it can be easily used in a newly designed logic circuit, and therefore the design of the logic circuit can be improved. can be carried out extremely efficiently.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the invention. FIG. 2 is an explanation of the system configuration of the embodiment. FIG. 3 is a block diagram explaining the embodiment. FIG. 4 is a diagram explaining the circuit display of the embodiment. 1 FIG. 5 (A) Fig. 5 (B) shows the truth table system of the partial circuit 1 Fig. 6 shows the explanation of the logical formula derivation action 1 Fig. 8 shows the content of the extraction range 1 Fig. 7 is a flowchart explaining the process of displaying the logical formula in the window , FIG. 9 is an explanatory diagram of a backtrace connection net table, and FIG. 10 is an explanation of a logical connection relation table 1. FIG. 11 is a block diagram illustrating a conventional technique. 10... Existing logic circuits 200, 202. 204. 206・Φ・Work stage Ron 208--Host computer 300...Database section 302--Conversion processing section 304.306...Conversion section 308...Logic entry processing section 310--Fist data input section 312 . . . Operation input section 314 . . . Editing section 316 -- Compression processing section 318 . 328... Library section 400.402.404... Areas 450, 452. 454-...Window] Ward 1 0 Figure 1 1

Claims (1)

[Claims] A representation format conversion means (12) for converting an existing logic circuit (10) into a functional level representation format, and an existing logic circuit (10) expressed in a functional level format. Input editing means (16) for input editing a new logic circuit (14)
), and a database registration means (20) for registering the target logic circuit (14) obtained by input editing in the database (18).
A logic circuit editing method characterized by having the following.