JPH0442690B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a microprogram-controlled computer, and particularly to a microprogram-controlled computer suitable for high-speed processing of movement instructions.

[Background of the invention]

As is well known, a move instruction is used to transfer (move) a group of data from one area to another area within main memory. The move command has the format shown in Figure 2, where the OP code is the instruction code indicating that it is a move command, L is the length of the data to be moved (movement amount - 1), and OP1 address is the move destination (first operand). The first address and OP2 address of
This is the start address of the movement source (second operand). By the way, reading and writing from main memory is done in units of 4 or 8 bytes, for example, whereas OP
1 address and OP2 address do not necessarily specify 4-byte boundaries or 8-byte boundaries, and similarly, depending on the length L, the final read position and write position may not always be on these byte boundaries.
In other words, it is necessary to perform alignment processing on the data read out from the memory and write it into the same memory.

Conventionally, movement instruction processing in a microprogram-controlled computer involves a read align circuit that aligns data read from memory and generates data to be written to memory, as described in Japanese Patent Application Laid-Open No. 59-123936. Data alignment was performed with the write align circuit. It also has a comparison circuit that compares the remaining movement amount with the data alignment amount, and when writing to the first operand in the final cycle, the output of the comparison circuit is checked by a microprogram, and the second operand data is read out again. It is determined whether the first operand is written later or the first operand is written without reading the second operand data.
However, in this method, the shift amount for data alignment is different for each align circuit, and the shift amount may change during processing, making the align circuit complicated. In addition, it is not possible to determine whether or not to read the second operand data before writing to the first operand in the final round, until the condition of writing the first operand in the final stage of processing is satisfied, which reduces the speed. This hinders the development of

[Purpose of the invention]

An object of the present invention is to simplify the structure of a microprogram in a microprogram-controlled computer and to realize high-speed and efficient processing of movement instructions.

[Summary of the invention]

In the present invention, the format of the processing order of reading and writing, including the format of the last time, is processed by each byte address part of the address information of OP1 and OP2 in the movement instruction and the value of length L, and the format of the processing order of the movement instruction is determined. The system branches to the microprogram routine most suitable for each format and executes the movement instruction. As a result, each microprogram routine simply needs to read and write according to its format, and in the middle of the process it is necessary to read the operand twice in succession, or write it without reading it. Since there is no need for judgment conditions such as whether or not the program should be performed (the only judgment condition required is whether or not it is the final round), the structure of the microprogram is simplified.
High-speed processing of movement commands becomes possible.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In addition, in this embodiment, memory reading/writing is performed in 4
Assume that this is done in bytes.

The processing format of the movement command is divided into four types as shown in FIG. In FIG. 3, R is read;
W indicates writing, and arrows indicate processing order. , Conditions A, B, and C are expressed by the following equations when reading and writing from memory is 4 bytes.

Condition A = (Lowest 2 bits of OP1 address) ≧ (Lowest 2 bits of OP2 address) Condition B = [(Lowest 2 bits of OP1 address) + (Lowest 2 bits of length)] ≧ 4 Condition C = [(Lowest 2 bits of OP2 address) Least significant 2 bits) + (Length least significant 2 bits)] < 4 For format 1, after reading the OP2 address data,
This is a case where the process is completed by repeating the operation of aligning and writing to the OP1 address. FIG. 4a shows an example of the first format. Format 2 is OP
This is a case in which after reading data from two addresses, the operation of aligning and writing to the OP1 address is repeated, and finally, only one write operation is performed to complete the process. An example of format 2 is shown in FIG. 4b. Format 3 is a case in which only the OP2 address/data read operation is performed the first time, and thereafter, after reading the OP2 address/data, the process is completed by repeating the operation of aligning and writing to the OP1 address. An example of format 3 is shown in FIG. 4c. Format 4 performs only the OP2 address/data read operation the first time, and thereafter, after reading the OP2 address/data, the OP2 address/data read operation is performed.
This is a case where the write operation is repeated in alignment with one address, and finally the process is completed by performing only one write operation. FIG. 4d shows an example of format 4. Note that the length is the value of "the number of bytes of data to be moved - 1".

FIG. 1 is a block diagram of an embodiment of the present invention, in which 1 is an OP1 address register, 2 is an OP2 address register, 3 is a length register, 4 is a comparison circuit, 5 and 6 are adder circuits, and 7 and 8 are comparison circuits. The circuits include a main memory 9, read data registers 10 and 11, an align circuit 12, a processing classification circuit 13, and a microprogram address generation circuit 14. In FIG. 1, the microprogram storage section (control memory) is omitted. 15 is OP1
Signal representing the lowest 2 bits of address register 1, 16 is the lowest 2 bits of OP2 address register 2
17 is a signal representing the lowest two bits of length register 3, 18 is a result output signal of comparison circuit 4, 19 is a result output signal of comparison circuit 7, 20 is a result output signal of comparison circuit 8, 21 ~2
4 is a signal representing each processing format 1 to 4 shown in FIG. Note that the bus width of the main memory 9 is 4 bytes.

The OP1 address, OP2 address and length L (movement amount -1) of the movement command are set in OP1 address register 1, OP2 address register 2 and length register 3, respectively.

Comparison circuit 4 compares the two least significant bits of OP1 address register 1 with the two least significant bits of OP2 address register 2. The addition circuit 5 is
The lowest two bits of the OP1 address register 1 and the lowest two bits of the length register 3 are added, and the comparison circuit 7 compares the result of the addition circuit 5 with a constant "4". The adder circuit 6 adds the two least significant bits of the OP2 address register 2 and the two least significant bits of the length register 3, and the comparator circuit 8 compares the result of the adder circuit 6 with a constant "4". Therefore, the result output signal 18 of the comparator circuit 4 is
The result output signal 19 of the comparison circuit 7 represents the condition A shown in FIG. 3, the result output signal 20 of the comparison circuit 8 represents the condition C shown in FIG. 3.

The align circuit 12 determines the amount of shift based on the two least significant bits of the OP1 address register 1 and the two least significant bits of the OP address register 2, and shifts the data in the read data registers 10 and 11 to create write data.

The classification circuit 13 selects one of the processing formats 1 to 4 shown in FIG. 3 from the signals 18, 19, and 20.
Therefore, the output signals 21 to 24 of the classification circuit 13 correspond to the processing formats shown in FIG. 3, respectively.

The microprogram address generation circuit 14 is
Output signals 21, 22, 23, of the classification circuit 13,
From 24, the start address of the microprogram routine that executes each processing format shown in FIG. 3 is generated. A control memory (not shown) stores microprogram routines for each processing format shown in FIG. ) is selected and executed.

Next, the operation will be described in detail according to the example shown in FIG. Fifth
In the example shown, the contents of OP1 address register 1 are 201, the contents of OP2 address register 2 are 103, and the contents of length register 3 are 8 (movement amount - 1). Therefore, signal 1
5 is “01”, signal 16 is “11”, signal 17 is “00”
become. Furthermore, the signal 18 becomes "0", and the signal 19 becomes "0".
becomes "0" and the signal 20 becomes "1". As a result, the outputs of the classification circuit 13 are such that the signals 21 to 23 become "0" and the signal 24 becomes "1". That is,
This is format 4 in FIG. 3, and the microprogram address generation circuit 14 generates the start address of the microprogram in format 4, and passes the processing to the microprogram control mechanism.

FIG. 6 is a processing flow diagram of microprograms corresponding to formats 1 to 4 in FIG. 3, but here, processing of a microprogram of format 4 will be explained according to the example of FIG.

First, as a first read operation, "MMMX" is read into the read data register 10. Next, repeated read and write operations are performed as follows. First, the OP2 address register 2 is incremented by 4, and data "YZDE" is read into the read data register 11. The data in read data registers 10 and 11 is shifted by two bytes to the left in the order of register 10 and register 11 by align circuit 12, and write data "MXYZ" is created. Then, "XYZ" is written to the 3 bytes starting from address 201 in the main memory. Thereafter, the contents of OP1 address register 1 are incremented by 4. Next, the contents of the OP2 address register 2 are incremented by 4 again.
Then, data “FGHI” is read into the read data register 10. At this time, the contents of the read data register 11 do not change. The data in the read data registers 10 and 11 is sent to the align circuit 12.
Therefore, the left 2 in the order of register 11 and register 10
Byte is performed, and write data "DEFG" is created. Then, "DEFG" is written into the 4 bytes starting from address 204 in the main memory 9. Then again
The contents of OP1 address register 1 are incremented by 4.
Then, the final write operation is performed as follows.
The data in read data registers 10 and 11 is transferred to register 10 and register 1 by alignment circuit 12.
1 is shifted 2 bytes to the left, and write data "HIYZ" is created. And main memory 9
"HI" is written to the 2 bytes after address 208, and the entire process is completed.

In this embodiment, the bus width of the main memory 9 is 4 bytes, but even if the bus width is different from this embodiment, if the processing classification conditions are changed according to the bus width,
The present invention is applicable.

This embodiment has a classification circuit 13 that performs processing classification, and the microprogram address is automatically determined based on the output of the classification circuit 13, so that branching to each processing microprogram can be performed at high speed.

〔Effect of the invention〕

As described above, in the present invention, the format of the processing order of reading and writing to the memory can be set to a plurality of formats depending on the lower predetermined bits of the first operand address field and the second operand address field and the values of the data length field in the move instruction. Classify and prepare microprogram routines for each format. Therefore, each microprogram routine has a simple structure that reads and writes according to its respective format (the judgment condition is at most whether it is the last time), and the microprogram is greatly simplified.
Furthermore, when executing a move instruction, at the beginning of the process, a branch is made to the desired microprogram routine according to the first and second operator address parts and data length part of the move instruction, and the rest is executed by the microprogram routine. Accordingly, it is only necessary to read and write according to each format, and there is no need to judge during processing whether or not to read the operan twice in succession, or whether to write without reading. Therefore, processing speed can be increased. Note that since the shift amount for data alignment is constant throughout processing, the hardware has the advantage that only one data alignment circuit is required.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
Figure 3 shows the processing format of movement commands, Figure 3 shows the processing methods of movement commands and their classification conditions, Figure 4 shows specific examples of each processing format, and Figure 5 shows specific examples of processing. FIG. 6 is a flow diagram of the microprogram. 1...First operand address register, 2...
...Second operand address register, 3...Length register, 4...Comparison circuit, 5...Addition circuit, 6...Addition circuit, 7...Comparison circuit, 8...Comparison circuit, 9...Main memory, 10 ... Read data register, 11 ... Read data register, 12
...Data alignment circuit, 13...Classification circuit, 1
4...Microprogram address generation circuit.

Claims (1)

[Scope of Claims] 1. A microprogram-controlled computer comprising a first operand address field, a second operand address field, and a data length field,
A move instruction that sequentially reads data of the data length indicated by the data length section in memory data width units from the memory address indicated by the operand address section, and sequentially writes data from the memory address indicated by the first operand address section. Format 1, in which the process is completed by repeating read and write operations; Format 2, in which the process is completed by repeating read and write operations, and only one write operation at the end; only the first read operation is performed; Format 3, in which the process is completed by repeating read and write operations, performs only one read operation at the beginning, then repeats read and write operations, and finally performs only one write operation. It is divided into four formats in which processing is completed, and microprogram routines are provided corresponding to each format, and the values of the lower predetermined bits and data length portion of the first operand address field and second operand address field of the movement instruction to be executed are divided into four formats. A microprogram comprising means for determining whether the processing method of the movement instruction corresponds to one of the formats 1 to 4, and means for branching to a microprogram routine of the corresponding format based on the determination result. Control computer.