JPH0442823B2 - - Google Patents
Info
- Publication number
- JPH0442823B2 JPH0442823B2 JP9044289A JP9044289A JPH0442823B2 JP H0442823 B2 JPH0442823 B2 JP H0442823B2 JP 9044289 A JP9044289 A JP 9044289A JP 9044289 A JP9044289 A JP 9044289A JP H0442823 B2 JPH0442823 B2 JP H0442823B2
- Authority
- JP
- Japan
- Prior art keywords
- nitride film
- oxidation
- region
- isolation
- epitaxial layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 claims description 42
- 230000003647 oxidation Effects 0.000 claims description 40
- 238000007254 oxidation reaction Methods 0.000 claims description 40
- 238000002955 isolation Methods 0.000 claims description 18
- 150000004767 nitrides Chemical class 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 9
- 238000000926 separation method Methods 0.000 claims description 4
- 238000005137 deposition process Methods 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 230000000873 masking effect Effects 0.000 claims 2
- 241000293849 Cordylanthus Species 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000010354 integration Effects 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Classifications
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F01—MACHINES OR ENGINES IN GENERAL; ENGINE PLANTS IN GENERAL; STEAM ENGINES
- F01B—MACHINES OR ENGINES, IN GENERAL OR OF POSITIVE-DISPLACEMENT TYPE, e.g. STEAM ENGINES
- F01B29/00—Machines or engines with pertinent characteristics other than those provided for in preceding main groups
- F01B29/08—Reciprocating-piston machines or engines not otherwise provided for
- F01B29/10—Engines
Landscapes
- Engineering & Computer Science (AREA)
- Mechanical Engineering (AREA)
- General Engineering & Computer Science (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は半導体素子分離法、特に半導体板上に
形成された複数の素子を互いに電気的に分離する
ための選択酸化法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device isolation method, and particularly to a selective oxidation method for electrically isolating a plurality of devices formed on a semiconductor substrate from each other.
[従来の技術]
半導体基板上に形成してなるバイポーラデバイ
スあるいはMOSトランジスタ等のユニポーラデ
バイスにおいては互いに電気的に絶縁された領域
に半導体素子を形成し回路を構成する。[Prior Art] In a bipolar device formed on a semiconductor substrate or a unipolar device such as a MOS transistor, semiconductor elements are formed in mutually electrically insulated regions to form a circuit.
各半導体素子を電気的に分離する方法としては
PN接合分離法が安価で容易な分離法として広く
用いられている。PN接合分離法は表面から深く
P形拡散層を基板に到達させ、基板および分離P
形領域を最低電位に保持する事により素子領域と
の間に形成されるPN接合を逆バイアスして素子
を電気的に分離する方法である。 As a method of electrically isolating each semiconductor element,
The PN junction separation method is widely used as an inexpensive and easy separation method. In the PN junction separation method, a P-type diffusion layer reaches deep from the surface to the substrate, and the substrate and separated P
This is a method of electrically isolating the device by holding the shape region at the lowest potential and reverse biasing the PN junction formed between the device region and the device region.
しかし、このPN接合分離法では分離領域と素
子の間隔をあまり狭められず、高集積を図ること
が困難であつた。 However, with this PN junction isolation method, the distance between the isolation region and the element cannot be narrowed very much, making it difficult to achieve high integration.
そこで、従来においては集積度を向上させるた
の1手法として選択酸化法が考えられていた。 Therefore, in the past, selective oxidation was considered as just one method for improving the degree of integration.
第4図にバイポーラデバイスを例にとり、従来
の選択酸化法を説明する断面図を示す。p形シリ
コン基板20上にコレクタ抵抗を低減するための
n+埋めこみ層22と素子分離用p+チヤネルカツ
ト層を24形成し(第4図A)その上にn形エピ
タキシヤル層26を成長させる。つぎに、応力緩
和のためにエピタキシヤル層26を薄く熱酸化し
た後マスク窒化膜28をCVDにより堆積する
(第4図B)。 FIG. 4 shows a cross-sectional view illustrating a conventional selective oxidation method using a bipolar device as an example. on the p-type silicon substrate 20 to reduce collector resistance.
An n + buried layer 22 and a p + channel cut layer 24 for device isolation are formed (FIG. 4A), and an n type epitaxial layer 26 is grown thereon. Next, the epitaxial layer 26 is thermally oxidized into a thin layer for stress relaxation, and then a mask nitride film 28 is deposited by CVD (FIG. 4B).
そして、分離すべき領域のマスク窒化膜28を
フツ化水素溶液等でエツチングし(第4図C)、
エピタキシヤル層26をp+チヤネルカツト層2
4に到達するまで熱酸化させ、第4図Dに示すよ
うに分離用の酸化領域30を形成することにより
エピタキシヤル層26に形成されるバイポーラ素
子を電気的に分離することができる。 Then, the mask nitride film 28 in the area to be separated is etched with a hydrogen fluoride solution or the like (FIG. 4C).
Epitaxial layer 26 as p + channel cut layer 2
The bipolar elements formed in the epitaxial layer 26 can be electrically isolated by thermally oxidizing the epitaxial layer 26 until the epitaxial layer 26 reaches the epitaxial layer 26, and forming an oxidized region 30 for isolation as shown in FIG. 4D.
このように、選択酸化法では分離領域と素子領
域との間隔をとる必要がなく、PN接合分離法に
比べて著しく高集積が可能となる。 In this way, with the selective oxidation method, there is no need to provide a gap between the isolation region and the element region, and it is possible to achieve a significantly higher degree of integration than with the PN junction isolation method.
[発明が解決しようとする課題]
しかしながら、従来の選択酸化法においては幾
つかの問題が生じていた。第5図に第4図Dの一
部拡大図を示す。前述したように、選択酸化法に
おいては酸化防止マスクとして窒化膜28を
CVDで堆積させる前に、応力緩和のために薄く
エピタキシヤル層26を熱酸化させてパツド酸化
膜32を形成しているが、分離用の酸化領域30
を形成する際にエピタキシヤル層26が酸化によ
り約2倍に体積膨張し、このため分離酸化領域3
0が素子形成領域に入り込んで前記パツド酸化膜
32と一体化し素子形成領域と分離酸化領域30
の境界をぼやけさせる、いわゆるバーズビーク3
4が発生して集積度の大幅な向上が図れないとい
う問題があつた。[Problems to be Solved by the Invention] However, several problems have arisen in the conventional selective oxidation method. FIG. 5 shows a partially enlarged view of FIG. 4D. As mentioned above, in the selective oxidation method, the nitride film 28 is used as an oxidation prevention mask.
Before being deposited by CVD, the thin epitaxial layer 26 is thermally oxidized to form a pad oxide film 32 for stress relaxation.
When forming the epitaxial layer 26, the volume expands approximately twice due to oxidation, and therefore the isolation oxidation region 3
0 enters the element formation region and is integrated with the pad oxide film 32, forming the element formation region and the isolation oxide region 30.
The so-called Bird's Beak 3 blurs the boundaries between
There was a problem that 4 occurred, making it impossible to achieve a significant improvement in the degree of integration.
本発明は上記従来の課題に鑑みなされたもので
あり、その目的は分離酸化領域を形成する際に生
じるバーズビークを抑制し、半導体素子が形成さ
れる素子形成領域を確実に分離して集積度を向上
することが可能な改良された選択酸化法を提供す
ることにある。 The present invention has been made in view of the above-mentioned conventional problems, and its purpose is to suppress bird's beaks that occur when forming isolated oxidation regions, and to reliably separate element formation regions where semiconductor elements are formed, thereby increasing the degree of integration. An object of the present invention is to provide an improved selective oxidation method that can be improved.
[課題を解決するための手段]
上記目的を達成するために、本発明は選択酸化
法において、第1図に示すように目標とする分離
酸化膜厚以下の膜厚まで酸化する第1酸化プロセ
ス10と、マスク窒化膜及び前記第1酸化プロセ
スにて形成された酸化領域をエツチングするエツ
チングプロセス12と、マスク窒化膜を再堆積す
る堆積プロセス14と、目標とする分離酸化膜厚
まで酸化する第2酸化プロセス16とを有したこ
とを特徴としている。[Means for Solving the Problems] In order to achieve the above object, the present invention employs a first oxidation process in which a film is oxidized to a thickness equal to or less than a target isolation oxide film thickness, as shown in FIG. 1, in a selective oxidation method. 10, an etching process 12 for etching the mask nitride film and the oxidized region formed in the first oxidation process, a deposition process 14 for redepositing the mask nitride film, and a first oxidation process for oxidizing the isolation oxide film to a target thickness. 2 oxidation process 16.
[作用]
本発明に係る選択酸化法は前述のプロセスを有
し、分離酸化領域を複数回の酸化プロセスで形成
する。[Operation] The selective oxidation method according to the present invention includes the above-described process, and the isolated oxidation region is formed by multiple oxidation processes.
即ち、第1酸化プロセスにて酸化された領域を
エツチングプロセスにてエツチングしマスク窒化
膜を堆積させると、このマスク窒化膜はエツチン
グ凹部のために素子形成領域の側壁部に回り込
み、この側壁部をも保護することになる。このた
め、第2酸化プロセスにて分離酸化領域を形成す
る際の酸化による素子形成領域方向への酸化領域
の膨張を防ぎバーズビークを抑制することができ
る。 That is, when the region oxidized in the first oxidation process is etched in the etching process and a mask nitride film is deposited, this mask nitride film wraps around the side wall portion of the element forming region due to the etching recess, and the side wall portion is will also be protected. Therefore, it is possible to prevent expansion of the oxidized region toward the element formation region due to oxidation when forming the isolated oxidized region in the second oxidation process, and to suppress bird's beak.
[実施例]
以下、図面を用いて本発明に係る半導体素子分
離用選択酸化法の好適な実施例をバイポーラデバ
イスを例にとり説明する。[Example] Hereinafter, a preferred example of the selective oxidation method for semiconductor element isolation according to the present invention will be described with reference to the drawings, taking a bipolar device as an example.
第2図は本発明に係る一実施例を説明する断面
図を示したものであり、第2図Aは従来と同様に
シリコン基板20にn+埋めこみ層22、p+チヤ
ネルカツト層24、エピタキシヤル層26、パツ
ド酸化膜、マスク窒化膜28を順次形成したとこ
ろを示す。なお、本実施例においてはエピタキシ
ヤル層26の厚さは500nmとした。 FIG. 2 shows a cross-sectional view for explaining one embodiment of the present invention, and FIG. 2A shows a silicon substrate 20 with an n + buried layer 22, a p + channel cut layer 24, and an epitaxial layer as in the conventional case. The sequential formation of layer 26, pad oxide film, and mask nitride film 28 is shown. In this example, the thickness of the epitaxial layer 26 was 500 nm.
従来の選択酸化法においては、前述したように
一度の酸化プロセスにてp+チヤネルカツト層2
4に達するまでエピタキシヤル層26を熱酸化さ
せて分離酸化領域を形成していたが、本発明は第
2図Bに示すようにまず目標とする分離酸化膜
厚、即ちp+チヤネルカツト層24に達する膜厚
の1/2以下の膜厚までエピタキシヤル層26を熱
酸化させるものであり、本実施例においては
200nm程度酸化させた。 In the conventional selective oxidation method, as mentioned above, the p + channel cut layer 2 is formed in one oxidation process.
However, as shown in FIG. This is to thermally oxidize the epitaxial layer 26 to a film thickness that is less than 1/2 of the achieved film thickness, and in this example,
It was oxidized to about 200 nm.
次に、マスク窒化膜28及び前述の第1酸化プ
ロセスにて形成されたエピタキシヤル層の酸化領
域をフツ化水素溶液を用いてエツチングした(第
2図C)。 Next, the mask nitride film 28 and the oxidized regions of the epitaxial layer formed in the first oxidation process described above were etched using a hydrogen fluoride solution (FIG. 2C).
そして再びパツド酸化膜32を形成した後マス
ク窒化膜28をCVDにより堆積させ(第2図
D)、分離すべき領域のマスク窒化膜のエツチン
グを行なつた(第2図E)。 After forming the pad oxide film 32 again, a mask nitride film 28 was deposited by CVD (FIG. 2D), and the mask nitride film in the region to be separated was etched (FIG. 2E).
このとき、第3図の拡大に示すようにマスク窒
化膜28は前述のエツチングプロセスにて形成さ
れたエピタキシヤル層26の凹部36に回り込ん
で素子形成領域の側壁部を保護している。従つ
て、この状態からエピタキシヤル層26をp+チ
ヤネルカツト層に達するまで第2酸化プロセスに
て熱酸化させると、素子形成領域への酸化領域の
膨張が阻止され、第2図Fに示すようにバーズビ
ークの極めて少ない分離酸化領域が形成されてい
ることがわさかる。 At this time, as shown in the enlarged view of FIG. 3, the mask nitride film 28 wraps around the recess 36 of the epitaxial layer 26 formed by the above-described etching process to protect the side wall portion of the element forming region. Therefore, if the epitaxial layer 26 is thermally oxidized in the second oxidation process from this state until it reaches the p + channel cut layer, the expansion of the oxidized region toward the element formation region is prevented, and as shown in FIG. 2F, It can be seen that an isolated oxidized region with very few bird's beaks is formed.
なお、本発明はエツチングプロセスにてエピタ
キシヤル層26に凹部36を形成して熱酸化させ
るため、酸化に伴なうエピタキシヤル層26の基
板上方向への膨張を補償して表面を平坦化してい
ることも第2図Fより明らかである。 In addition, in the present invention, since the recesses 36 are formed in the epitaxial layer 26 by an etching process and thermally oxidized, the expansion of the epitaxial layer 26 in the upward direction of the substrate due to oxidation is compensated for and the surface is flattened. It is also clear from Figure 2 F that there are
なお、本実施例においてはバイポーラデバイス
を例にとり説明したが、これに限定されるもので
はなく、MOSトランジスタ等のユニポーラデバ
イスにも適用することができる。 Note that although this embodiment has been described using a bipolar device as an example, the invention is not limited to this, and can also be applied to unipolar devices such as MOS transistors.
[発明の効果]
以上説明したように、本発明に係る選択酸化法
よれば、分離酸化領域を形成する際に生じるバー
ズビークを抑制することができ、素子を確実に分
離して集積度を向上させることが可能となる。[Effects of the Invention] As explained above, according to the selective oxidation method according to the present invention, it is possible to suppress bird's beaks that occur when forming isolated oxidation regions, and to reliably separate elements and improve the degree of integration. becomes possible.
また、本発明は酸化に伴なう体積膨張をエツチ
ングプロセスにて補償しているため、素子分離後
の表面をほぼ平坦化することができ、このため素
子分離後の後工程、例えばアルミ配線工程が容易
に行なえるので生産効率を高める効果も有する。 In addition, since the present invention compensates for the volumetric expansion caused by oxidation through the etching process, the surface after element isolation can be made almost flat, which makes it possible to substantially flatten the surface after element isolation, such as the aluminum wiring process. Since it can be easily carried out, it also has the effect of increasing production efficiency.
第1図は本発明に係る半導体素子分離用選択酸
化法のフローチヤート図、第2図は本発明の一実
施例を説明する断面図、第3図は第2図の一部を
拡大した断面図、第4図は従来の選択酸化法を説
明する断面図、第5図は第4図の一部を拡大した
断面図である。
10……第1酸化プロセス、12……エツチン
グプロセス、14……堆積プロセス、16……第
2酸化プロセス、20……シリコン基板、26…
…エピタキシヤル層、28……p+チヤネルカツ
ト層、34……バーズビーク。
FIG. 1 is a flowchart of a selective oxidation method for semiconductor element isolation according to the present invention, FIG. 2 is a cross-sectional view illustrating an embodiment of the present invention, and FIG. 3 is a cross-sectional view of a portion of FIG. FIG. 4 is a cross-sectional view illustrating a conventional selective oxidation method, and FIG. 5 is an enlarged cross-sectional view of a part of FIG. 4. DESCRIPTION OF SYMBOLS 10... First oxidation process, 12... Etching process, 14... Deposition process, 16... Second oxidation process, 20... Silicon substrate, 26...
...Epitaxial layer, 28...P + channel cut layer, 34...Bird's beak.
Claims (1)
に分離する酸化領域を形成するための選択酸化法
において、 目標とする分離酸化膜厚以下の膜厚まで窒化膜
によりマスクして酸化する第1酸化プロセスと、 前記マスク窒化膜及び前記第1酸化プロセスに
て形成した酸化領域をエツチングするエツチング
プロセスと、 マスク窒化膜を再堆積する堆積プロセスと、 目標とする分離酸化膜厚まで前記マスク窒化膜
によりマスクして酸化する第2酸化プロセスと、
を有し、素子分離用の酸化領域を複数回の酸化プ
ロセスで形成することにより正確に半導体素子を
分離することができることを特徴とする半導体素
子分離用選択酸化法。[Scope of Claims] 1. In a selective oxidation method for forming an oxidized region that electrically isolates a semiconductor element formed on a semiconductor substrate, masking with a nitride film to a thickness equal to or less than a target isolation oxide film thickness is performed. an etching process for etching the mask nitride film and the oxidized region formed in the first oxidation process; a deposition process for redepositing the mask nitride film; and a target separation oxide film thickness. a second oxidation process of masking and oxidizing with the mask nitride film until
1. A selective oxidation method for semiconductor device isolation, characterized in that a semiconductor device can be accurately separated by forming an oxidized region for device isolation in a plurality of oxidation processes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9044289A JPH02268435A (en) | 1989-04-10 | 1989-04-10 | Selective oxidation for isolation of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9044289A JPH02268435A (en) | 1989-04-10 | 1989-04-10 | Selective oxidation for isolation of semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02268435A JPH02268435A (en) | 1990-11-02 |
| JPH0442823B2 true JPH0442823B2 (en) | 1992-07-14 |
Family
ID=13998734
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9044289A Granted JPH02268435A (en) | 1989-04-10 | 1989-04-10 | Selective oxidation for isolation of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02268435A (en) |
-
1989
- 1989-04-10 JP JP9044289A patent/JPH02268435A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02268435A (en) | 1990-11-02 |
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