JPS6037614B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides lop (Isolation by Oxi)
de &Pol$ilicon) or VIP (Vee-
Isolation MthPolore iliconBa
The present invention relates to a method of manufacturing a semiconductor device that performs isolation and insulation between elements using a technique called ck-fill (hereinafter referred to as lOP).

Generally, in a semiconductor device in which element isolation is performed using the IOP method, it is possible to align the base region and emitter region with the isolation region, so the area occupied by the element can be reduced and the degree of integration can be increased. can be improved.

FIG. 1 is an explanatory diagram of the main parts of a bipolar semiconductor device manufactured by applying the IOP method.

In the figure, 1 is a p-type silicon semiconductor substrate, 2 is an n-type silicon epitaxial layer, 3 is a silicon dioxide film, and 4 is a p-type silicon semiconductor substrate.
is a polycrystalline silicon layer, 5 is a p-type base region, 6 is an n+ type emitter region, 7 is an n+ collector contact region, 8
indicate the base contact area, respectively.

Incidentally, in semiconductor devices having this structure, it has been a problem that collector-emitter (CB) short circuits are likely to occur.

The reason for this is the process of manufacturing the emitter region using a self-alignment method.

This will be explained with reference to FIGS. 2 to 5. Refer to FIG. 2 (1). The figure shows a state in which the base region forming window 38 has been formed.

The symbols for each part shall be as shown in FIG. 1. Furthermore, symbol 3
' indicates a step created by forming the window 38 by self-isolation. Refer to FIG. 3 '2} A p-type impurity is diffused from the window 3B using a thermal diffusion method to form a p-type base region 5.

At this time, the window 3B is covered with a silicon dioxide film 3A. See Figure 4. On the isolation region side, pattern the silicon dioxide film 3A for self-alignment.
An emitter forming window 3E is formed.

Incidentally, the symbol 3'' indicates a level difference caused by forming the window 3E using the self-alignment method. By the way, in this step, not only the formation of the window 38 but also the base contamination window and the collector window 38 are formed. A contact window (not shown) is also formed.

Generally, when forming the collector contact window, the thickest silicon dioxide film must be removed. Therefore, while performing the etching, the etching of the window 3E is caused by the V formed in the silicon epitaxial layer 2.
Proceeds along the cut groove in the depth direction. Refer to FIG. 6 {4} Polycrystalline silicon layer 9 and phosphosilicate glass layer 10 are formed by chemical vapor deposition, and heat treatment is performed to perform so-called through-diffusion of phosphorus contained in phosphosilicate glass layer 101. Then, an n+ type emitter region 6 is formed.

Then, phosphorus is deeply diffused along the V-cut groove, and C.
E short circuit will occur. The present invention prevents C/E short circuit from occurring even if the emitter region of a semiconductor device in which an isolation region is formed by the IOP method is formed by a self-alignment method, and this will be explained in detail below. . FIGS. 6 to 12 show the process sequence of the embodiment of the present invention, and will be described next with reference to these figures.

Refer to FIG. 6 '1' The diagram shows a state in which an isolation region is formed by applying the IPO method.

Note that 12 represents an n-type silicon epitaxial layer, 13 represents a silicon dioxide film, and 14 represents a polycrystalline silicon layer. Further, the surface of the epitaxial layer 12 is exposed by etching so that, for example, no silicon dioxide film is present on the surface of the element formation region. Refer to FIG. 7 [2] For example, by applying chemical vapor deposition method, the polycrystalline silicon layer 15 (first polycrystalline silicon layer) is grown to a thickness of, for example, ~5.
00 [A].

See Figure 8 [3} Selectively form a photoresist film 16.

(2) Applying the ion implantation method, shelf ions are introduced into the epitaxial layer 12 to form the p-type base region 17.
Note that instead of the step '3' and (2), the p-type base region 17 may be formed by diffusing boron by thermal diffusion using the silicon dioxide film as a mask. See FIG. 9. For example, by applying chemical vapor deposition, the silicon nitride film 18 is formed to a thickness of, for example, about 2000 [A].

(6) The silicon nitride film 18 is selectively etched using a normal photo-etching method to form the oxidation window 18.
Form A.

Referring to FIG. 10, heat treatment is performed in an oxidizing atmosphere to oxidize a portion of the polycrystalline silicon layer 15 and a portion of the epitaxial layer 12 to form a silicon dioxide film 13'.

See Figure 11 {8} Remove the exposed silicon film 18.

■ For example, by applying chemical vapor deposition, the polycrystalline silicon layer 19 (second polycrystalline silicon layer) is
] Form to a certain extent.

'10 Similarly, a phosphosilicate glass film 20 (impurity-doped oxide film) is formed by applying the chemical vapor deposition method.

(11) The scaly silicate glass film 20 is patterned using a conventional photo-etching method, and the portion above the base contact region is removed. Refer to FIG. 12 (12) Heat treatment is performed to diffuse phosphorus which is incorporated into the phosphosilicate glass film 20 through the polycrystalline silicon layers 19 and 15, thereby forming the n+ type emitter region 21 and the collector contact region 22. Form.

Thereafter, electrode wiring and the like are formed through normal steps.

As can be seen from the above description, according to the present invention, since the emitter region forming window is not formed by etching, the emitter region extends along the V-cut groove formed in the semiconductor bulk and is short-circuited with the collector region. There's nothing to do.

Therefore, a semiconductor device with high collector-emitter breakdown voltage and high integration can be easily manufactured. It should be noted that the present invention can also be applied to the self-alignment process in general oxide film buried isolation methods such as the well-known isoplanar method, in addition to the IOP method of the above embodiment, and the same effects as described above can be obtained. Needless to say.

[Brief explanation of drawings]

Figures 1 to 5 are explanatory diagrams of conventional examples, and Figures 6 to 12 are illustrations of conventional examples.
The figures each represent a process explanatory diagram of an embodiment of the present invention. In the figure, 12 is an epitaxial layer, 13 is a silicon dioxide film, 14 is a polycrystalline silicon layer, 15 is a polycrystalline silicon layer, 16 is a photoresist film, 17 is a base region, 18 is a silicon nitride film, 19 is a polycrystalline silicon layer, 2
0 represents a phosphosilicate glass film, 21 represents an emitter region, and 22 represents a collector contact region. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12

Claims (1)

[Claims] 1. A first polycrystalline silicon layer is formed on a semiconductor substrate having an isolation region for separating element formation regions in which an oxide film is embedded, and then at least one end is self-contained in the isolation region. Impurities are introduced for alignment to form a base region, and then the first
A silicon nitride film is formed on the entire surface of the polycrystalline silicon layer except for a portion to be selectively oxidized, and then, using the silicon nitride film as a mask for selective oxidation, at least the first polycrystalline silicon layer is selectively oxidized. Without silicon dioxide film,
Next, after removing the silicon nitride film used as the selective oxidation mask, a second polycrystalline silicon layer is formed,
Next, an impurity-doped oxide film is formed on the second polycrystalline silicon layer except for at least a portion corresponding to the base contact region, and then, using the silicon dioxide film as a mask, at least one end is formed in the isolation region. 1. A method of manufacturing a semiconductor device, comprising a step of introducing impurities for self-alignment to form an emitter region and a collector contact region.