JPH0442907Y2 - - Google Patents
Info
- Publication number
- JPH0442907Y2 JPH0442907Y2 JP11874186U JP11874186U JPH0442907Y2 JP H0442907 Y2 JPH0442907 Y2 JP H0442907Y2 JP 11874186 U JP11874186 U JP 11874186U JP 11874186 U JP11874186 U JP 11874186U JP H0442907 Y2 JPH0442907 Y2 JP H0442907Y2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- multilayer ceramic
- ceramic capacitor
- type multilayer
- exposed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003985 ceramic capacitor Substances 0.000 claims description 27
- 239000003990 capacitor Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000000919 ceramic Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011230 binding agent Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000009191 jumping Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
Landscapes
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Description
【考案の詳細な説明】
〔産業上の利用分野〕
本考案はチツプ型積層セラミツクコンデンサに
関し、特に1個にコンデンサとジヤンパー素子の
2役の特性を付与したチツプ型積層セラミツクコ
ンデンサに関する。[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a chip-type multilayer ceramic capacitor, and more particularly to a chip-type multilayer ceramic capacitor that has dual characteristics as a capacitor and a jumper element.
第3a図は従来のチツプ型積層セラミツクコン
デンサの斜視図、第3b図は従来のチツプ型積層
セラミツクスコンデンサの接続図である。
FIG. 3a is a perspective view of a conventional chip-type multilayer ceramic capacitor, and FIG. 3b is a connection diagram of a conventional chip-type multilayer ceramic capacitor.
従来、この種のチツプ型積層セラミツクコンデ
ンサは、第3a,b図に示すようにチツプ型積層
セラミツクコンデンサ5の対向する両端面に外部
電極11を設け、チツプ型積層セラミツクコンデ
ンサ1個についてひとつの容量を引出す構造とな
つている。 Conventionally, this type of chip-type multilayer ceramic capacitor has been provided with external electrodes 11 on both opposing end surfaces of the chip-type multilayer ceramic capacitor 5, as shown in FIGS. The structure is designed to draw out.
〔考案が解決しようとする問題点〕
上述した従来のチツプ型積層セラミツクコンデ
ンサは、コンデンサとしての機能を有するのみで
あるためチツプ型ジヤンパー素子は別に用意しな
ければならない。そのため2種類とも調達する必
要が生じて管理業務が煩雑となるほか、実装密度
向上の点でも限度があるという欠点がある。[Problems to be solved by the invention] Since the conventional chip-type multilayer ceramic capacitor described above only functions as a capacitor, a chip-type jumper element must be prepared separately. Therefore, it becomes necessary to procure both types, which complicates management work, and there is also a drawback in that there is a limit to the improvement in packaging density.
上述した従来のチツプ型積層セラミツクコンデ
ンサに対し、本考案は、コンデンサに配線部を飛
び越えて接続するジヤンパー線の役目を付加し、
1個でコンデンサとジヤンパー素子の2役の可能
な独創的内容を有するチツプ型積層セラミツクコ
ンデンサを提供することを目的とするものであ
る。 In contrast to the conventional chip-type multilayer ceramic capacitors mentioned above, the present invention adds the role of a jumper wire that connects the capacitor by jumping over the wiring,
The object of the present invention is to provide a chip-type multilayer ceramic capacitor having an original feature that allows one piece to serve as both a capacitor and a jumper element.
本考案のチツプ型積層セラミツクコンデンサ
は、矩形誘電体グリーンシート上に四辺のうち一
辺のみが端部まで露出する内部電極を被着し該被
着シートを互に180度方向を反転させて積層した
積層体と、矩形誘電体グリーンシート上に四辺の
うち対向する一対の両端面に露出する内部電極を
被着し積層した積層体とをそれぞれの内部電極の
露出した一対の端面同志の相対位置が90度となる
ように一体形成して焼結し内部電極が露出する四
端面に外部電極を設けて構成される。
The chip-type multilayer ceramic capacitor of the present invention has an internal electrode coated on a rectangular dielectric green sheet with only one of the four sides exposed to the end, and the sheets are stacked with their directions reversed by 180 degrees. A laminate and a laminate in which a rectangular dielectric green sheet is coated with internal electrodes exposed on both end faces of a pair of opposite sides of the four sides are stacked, and the relative positions of the pair of exposed end faces of each internal electrode are It is formed integrally and sintered so that the angle is 90 degrees, and external electrodes are provided on the four end faces where the internal electrodes are exposed.
次に本考案について図面を参照して詳細に説明
する。
Next, the present invention will be explained in detail with reference to the drawings.
第1a図は本考案のチツプ型積層セラミツクコ
ンデンサの一実施例の斜視図、第1b図は第1a
図のチツプ型積層セラミツクコンデンサのA−A
線およびB−B線断面図、第2a,2bおよび2
c図はそれぞれ第1a図のチツプ型積層セラミツ
クコンデンサの分解斜視図、積層体斜視図および
接続図である。 Figure 1a is a perspective view of an embodiment of the chip-type multilayer ceramic capacitor of the present invention, and Figure 1b is a perspective view of an embodiment of the chip-type multilayer ceramic capacitor of the present invention.
A-A of the chip-type multilayer ceramic capacitor in the figure
line and BB line cross-sectional views, 2a, 2b and 2
Figure c is an exploded perspective view, a perspective view of a laminate, and a connection diagram of the chip type multilayer ceramic capacitor shown in Figure 1a, respectively.
第2a図において、印刷済誘導体シート1A
は、矩形セラミツク誘電体シートの片面にAg/
Pd等の導体ペーストをスクリーン印刷法によつ
て被着し、矩形状の内部電極10の端部、内部電
極端部10aが矩辺方向に露出したものである。
また、印刷済誘導体シート1Bも上述した内容と
同一の手段により矩形セラミツク誘電体シートに
導体ペースと被着し内部電極20の端部、内部電
極端部20aが長手方向2辺として露出したもの
である。このとき、露出される内部電極端部10
a,20aは矩形誘導体シートの角部から離間さ
せる。次に、この印刷済誘電体シート1a順次一
枚づつ互いに180度方向を反転しながら積層し、
その後印刷済誘導シート1Bを積層する。さら
に、この上下に保護層となる複数板の誘電体シー
トを積層する。以上のようにして積層した誘電体
シートを熱プレス機で熱圧着し、第2b図に示す
積層体3を得る。次に、この積層体3の4つの端
面を形成し内部電極10aと20aが露出してい
る部分に4つの角部4から離隔させAg/Pdなど
の導体ペーストで外部電極を形成し、熱処理後脱
バインダー処理を施して焼成しチツプ型積層セラ
ミツクコンデンサ5を得る。第1a図はかくして
形成されたチツプ型積層セラミツクコンデンサ5
の斜視図であり、第1b図はその断面図、第2c
図は接続図を示し、外部電極11はジヤンパー素
子の電極を、また外部電極12はコンデンサの電
極として利用される。 In FIG. 2a, printed derivative sheet 1A
is a rectangular ceramic dielectric sheet with Ag/
A conductive paste such as Pd is applied by screen printing, and the end portions of the rectangular internal electrodes 10 and internal electrode end portions 10a are exposed in the rectangular direction.
The printed dielectric sheet 1B is also a rectangular ceramic dielectric sheet that is adhered to a conductor paste by the same means as described above, and the ends of the internal electrodes 20 and the internal electrode ends 20a are exposed as two sides in the longitudinal direction. be. At this time, the exposed internal electrode end 10
a and 20a are spaced apart from the corners of the rectangular dielectric sheet. Next, the printed dielectric sheets 1a are stacked one by one while reversing their directions by 180 degrees.
Thereafter, printed guidance sheets 1B are laminated. Furthermore, a plurality of dielectric sheets serving as protective layers are laminated above and below this. The dielectric sheets laminated as described above are bonded by thermocompression using a hot press machine to obtain a laminate 3 shown in FIG. 2b. Next, the four end faces of this laminate 3 are formed, and external electrodes are formed on the exposed portions of the internal electrodes 10a and 20a with a conductive paste such as Ag/Pd at a distance from the four corners 4, and after heat treatment. A chip-type multilayer ceramic capacitor 5 is obtained by performing binder removal treatment and firing. FIG. 1a shows a chip-type multilayer ceramic capacitor 5 thus formed.
FIG. 1b is a sectional view thereof, and FIG. 2c is a perspective view thereof.
The figure shows a connection diagram, and the external electrode 11 is used as an electrode of a jumper element, and the external electrode 12 is used as an electrode of a capacitor.
以上説明したように本考案によれば、チツプ型
積層セラミツクコンデンサ1個でコンデンサとジ
ヤンパー素子の2役をかねる構造とすることによ
り、部品の発注、納入、在庫管理業務の著しい簡
略化が可能となるとともに、また搭載部品の実装
密度の向上にも大幅に寄与しうるチツプ型積層セ
ラミツクコンデンサが実現できるという効果があ
る。
As explained above, according to the present invention, by creating a structure in which a single chip-type multilayer ceramic capacitor serves as both a capacitor and a jumper element, it is possible to significantly simplify parts ordering, delivery, and inventory control operations. In addition, there is an effect that a chip-type multilayer ceramic capacitor can be realized which can greatly contribute to improving the mounting density of mounted components.
第1a図は本考案のチツプ型積層セラミツクコ
ンデンサの一実施例の斜視図、第1b図は第1a
図のチツプ型積層セラミツクコンデンサのA−A
線およびB−B線断面図、第2a,2bおよび2
c図はそれぞれ第1a図のチツプ型積層セラミツ
クコンデンサの分解斜視図、積層体斜視図および
接続図、第3a図は従来のチツプ型積層セラミツ
クコンデンサの斜視図、第3b図は従来のチツプ
型積層セラミツクコンデンサの接続図である。
1A,1B……印刷済誘電体シート、3……積
層体、4……角部、5……チツプ型積層セラミツ
クコンデンサ、10,20……内部電極、10
a,20a……内部電極端部、11,12……外
部電極。
Figure 1a is a perspective view of an embodiment of the chip-type multilayer ceramic capacitor of the present invention, and Figure 1b is a perspective view of an embodiment of the chip-type multilayer ceramic capacitor of the present invention.
A-A of the chip-type multilayer ceramic capacitor in the figure
line and BB line cross-sectional views, 2a, 2b and 2
Figure c is an exploded perspective view, a perspective view and a connection diagram of the chip-type multilayer ceramic capacitor shown in Figure 1a, Figure 3a is a perspective view of a conventional chip-type multilayer ceramic capacitor, and Figure 3b is a conventional chip-type multilayer ceramic capacitor. It is a connection diagram of a ceramic capacitor. 1A, 1B... Printed dielectric sheet, 3... Laminate, 4... Corner, 5... Chip type multilayer ceramic capacitor, 10, 20... Internal electrode, 10
a, 20a...inner electrode end, 11, 12...external electrode.
Claims (1)
のみが端部まで露出する内部電極を被覆し該被着
シートを互に180度方向を反転させて積層した積
層体と、矩形誘電体グリーンシート上に四辺のう
ち対向する一対の両端面に露出する内部電極を被
着し積層した積層体とをそれぞれの内部電極の露
出した一対の端面同志の相対位置が90度となるよ
うに一体形成して焼結し内部電極が露出する四端
面に外部電極を設けたことを特徴とするチツプ型
積層セラミツクコンデンサ。 A laminate in which internal electrodes with only one of the four sides exposed to the end are covered on a rectangular dielectric green sheet, and the covered sheets are stacked with their directions reversed by 180 degrees, and a rectangular dielectric green sheet A laminate in which exposed internal electrodes are adhered to both end faces of a pair of opposing sides among the four sides is integrally formed and baked so that the relative positions of the exposed end faces of each internal electrode are 90 degrees. A chip-type multilayer ceramic capacitor characterized in that external electrodes are provided on the four end faces where the internal electrodes are exposed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11874186U JPH0442907Y2 (en) | 1986-07-31 | 1986-07-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11874186U JPH0442907Y2 (en) | 1986-07-31 | 1986-07-31 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6324821U JPS6324821U (en) | 1988-02-18 |
| JPH0442907Y2 true JPH0442907Y2 (en) | 1992-10-12 |
Family
ID=31005483
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11874186U Expired JPH0442907Y2 (en) | 1986-07-31 | 1986-07-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0442907Y2 (en) |
-
1986
- 1986-07-31 JP JP11874186U patent/JPH0442907Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6324821U (en) | 1988-02-18 |
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