JPH0442960A - Programmable element of semiconductor integrated circuit - Google Patents
Programmable element of semiconductor integrated circuitInfo
- Publication number
- JPH0442960A JPH0442960A JP2147848A JP14784890A JPH0442960A JP H0442960 A JPH0442960 A JP H0442960A JP 2147848 A JP2147848 A JP 2147848A JP 14784890 A JP14784890 A JP 14784890A JP H0442960 A JPH0442960 A JP H0442960A
- Authority
- JP
- Japan
- Prior art keywords
- film
- projecting part
- lower electrode
- cathode
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000009792 diffusion process Methods 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 2
- 238000002955 isolation Methods 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 abstract 1
- 230000005684 electric field Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体集積回路に組み込まれた電気的にプロ
グラム可能なプログラマブル素子に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to electrically programmable elements incorporated in semiconductor integrated circuits.
従来の技術
半導体集積回路のうち、使用者が購入した後に内容を電
気的に書き込むことのできるいわゆるF ROM (P
rogrammable RO)[)は望む内容のRO
M(Read 0nly Memory)がただちに得
られるためにひろく用いられている。Among conventional semiconductor integrated circuits, so-called F ROM (PROM) can be electrically written with contents after the user purchases them.
rogrammable RO) [) is the RO with the desired content
M (Read Only Memory) is widely used because it can be obtained immediately.
また論理回路の分野においても、やはり使用者が購入し
た後に内容を電気的に書き込むことのできるいわゆるP
L D (Programmable Logic
Device)が類似の目的のため用いられている。P
RCMやPLDを構成するためには外部から記憶内容が
電気的に書き込め、かつ電源を切ってもその記憶内容が
保持されるようなプログラマブル素子を用いる必要があ
る。Also, in the field of logic circuits, so-called P-type circuits that allow the user to electrically write the contents after purchasing the
L D (Programmable Logic
Device) is used for similar purposes. P
In order to configure an RCM or a PLD, it is necessary to use a programmable element that allows storage contents to be written electrically from the outside and that retains the storage contents even when the power is turned off.
従来このようなプログラマブル素子に好適な構造は例え
ば以下に示すようなものであった。Conventionally, a structure suitable for such a programmable element is as shown below, for example.
第2図は従来例のプログラマブル素子の構造を示す断面
図であり、これを参照]7て説明する。FIG. 2 is a sectional view showing the structure of a conventional programmable element.
図示するように、P型半導体基板1]がフィールド酸化
膜12により分離されており、分離された一領域中に下
部電極となる高不純物濃度の拡散層13が形成されてい
る。As shown in the figure, a P-type semiconductor substrate 1 is separated by a field oxide film 12, and a highly impurity-concentrated diffusion layer 13 serving as a lower electrode is formed in one separated region.
拡散層13上には厚さ1Onm程度の酸化物層14と多
結晶シリコンからなる上部電極15とか順次積層されて
形成されており、プログラミングは上部電極15と拡散
層13との間に20V程度の電圧を印加し、酸化物層1
4の絶縁を破壊して、上部電極15と拡散層13とを電
気的に導通させることによりおこなわれる。An oxide layer 14 with a thickness of about 1 Onm and an upper electrode 15 made of polycrystalline silicon are sequentially laminated on the diffusion layer 13, and programming is performed by applying a voltage of about 20V between the upper electrode 15 and the diffusion layer 13. Apply voltage, oxide layer 1
This is done by breaking the insulation of 4 and making the upper electrode 15 and the diffusion layer 13 electrically conductive.
発明が解決しようとする課題
一般に、上記のような従来例のプログラマブル素子にお
いて、プログラム時に印加する電圧をなるべ(低くする
ためには薄い絶縁膜が必要となり、プログラマブル素子
部分の容量が大きくなる。その結果、遅延時間が長くな
って動作速度が遅くなるという課題が生じる。Problems to be Solved by the Invention In general, in conventional programmable elements such as those described above, in order to lower the voltage applied during programming, a thin insulating film is required, which increases the capacitance of the programmable element portion. As a result, a problem arises in that the delay time becomes longer and the operating speed becomes slower.
課題を解決するための手段
上記のような課題を解決するための本発明のプログラマ
ブル素子は、厚い分離酸化物層により複数の領域に分割
された一導電型半導体基板中に形成された前記基板より
も高不純物濃度でかつ反対導電型の拡散層からなる下部
電極と、前記下部電極上に形成された絶縁膜と、前記絶
縁膜上に形成された上部電極とを備え、前記下部電極ま
たは前記上部電極のうち陰極として用いる電極の前記絶
縁膜と接する面に凸部が形成されている構造のものであ
る。Means for Solving the Problems The programmable element of the present invention for solving the above-mentioned problems is formed in a semiconductor substrate of one conductivity type divided into a plurality of regions by a thick isolation oxide layer. The lower electrode includes a diffusion layer having a high impurity concentration and an opposite conductivity type, an insulating film formed on the lower electrode, and an upper electrode formed on the insulating film, and the lower electrode or the upper Among the electrodes, the electrode used as a cathode has a structure in which a convex portion is formed on the surface in contact with the insulating film.
作用
本発明のプログラマブル素子では、プログラムされる絶
縁膜と接している陰極側電極に凸部があるため、上下電
極間に電圧印加した時電界の集中が起こる。このため電
子が陰極から絶縁膜中へ放出され易くなり、厚い膜でも
低い電圧でプログラムできることになる。つまり、同じ
書き込み電圧の下では絶縁膜厚を厚くでき、その結果絶
縁容量を小さくすることかで−きるようになる。従って
遅延時間は短くなり、動作速度が速くなるというもので
ある。Operation In the programmable element of the present invention, since the cathode side electrode in contact with the insulating film to be programmed has a convex portion, electric field concentration occurs when a voltage is applied between the upper and lower electrodes. Therefore, electrons are easily released from the cathode into the insulating film, and even a thick film can be programmed with a low voltage. In other words, under the same write voltage, the thickness of the insulating film can be increased, and as a result, the insulating capacitance can be reduced. Therefore, the delay time becomes shorter and the operating speed becomes faster.
実施例
本発明のプログラマブル素子の実施例を第1図に示し、
これを参照して説明する。Embodiment An embodiment of the programmable element of the present invention is shown in FIG.
This will be explained with reference to this.
第1図に示すように、P型シリコンの基板1がフィール
ド酸化膜2により複数の領域に分離されており、−領域
中に陰極として用いる下部電極であるN°°拡散層3が
形成されている。N゛型型数散層3は表面にフォトエツ
チング法によって凸部4か形成されており、その上部は
酸化膜5によって覆われている。酸化膜5の上には多結
晶/リコンからなる上部電極6が形成されている。酸化
膜5の膜厚はたとえば3Onm程度であるか、下部電極
3に負電圧を印加した際の耐圧は凸部を形成することに
より凸部の形、状等によっても異なるが1/3程度にな
るので、平坦部上の1On、m程度の膜と同程度の電圧
でプログラムできることになる。この凸部は容量とほと
んど無関係であり、プログラマブル素子の容量は凸部が
ないときの容量の1/3程度になっている。また、逆方
向の耐圧は電界の集中が電子の放出に作用しないので、
凸部がないときの耐圧と同程度となる。As shown in FIG. 1, a P-type silicon substrate 1 is separated into a plurality of regions by a field oxide film 2, and an N° diffusion layer 3, which is a lower electrode used as a cathode, is formed in the − region. There is. A convex portion 4 is formed on the surface of the N-type scattering layer 3 by photoetching, and the upper portion thereof is covered with an oxide film 5. An upper electrode 6 made of polycrystalline/licon is formed on the oxide film 5. The thickness of the oxide film 5 is, for example, about 3 Onm, or the withstand voltage when a negative voltage is applied to the lower electrode 3 is about 1/3 due to the formation of the convex part, although it varies depending on the shape and form of the convex part. Therefore, programming can be performed with the same voltage as a film of about 1 On.m on a flat part. This protrusion has almost no relation to capacitance, and the capacitance of the programmable element is about 1/3 of the capacitance without the protrusion. In addition, withstand voltage in the reverse direction, concentration of electric field does not affect electron emission, so
The withstand voltage is about the same as when there is no convex part.
なお、上記の実施例では説明の都合上N“拡散層3を陰
極としたが、これは実施例の構成に従う必要はなく、上
部電極6の下部に凸部を持たせ陰極としてもよい。In the above embodiment, the N'' diffusion layer 3 was used as a cathode for convenience of explanation, but it is not necessary to follow the structure of the embodiment, and a convex portion may be provided at the bottom of the upper electrode 6 to serve as a cathode.
発明の効果
本発明のプログラマブル素子では、陰極のプログラムさ
れる絶縁膜に接した面に凸部を形成した結果、絶縁耐圧
を凸部がない場合と同程度にしたまま、絶縁膜の厚さだ
けを厚くすることかできる。したがって、それに応して
絶縁容量も凸部かない場合に比べて小さくなり、書き込
み電圧を変えることなく遅延時間を短くするqとができ
る。Effects of the Invention In the programmable element of the present invention, as a result of forming a convex portion on the surface of the cathode that is in contact with the insulating film to be programmed, the dielectric strength is maintained at the same level as when there is no convex portion, but the thickness of the insulating film is reduced. It is possible to make it thicker. Therefore, the insulating capacitance is correspondingly smaller than that without the convex portion, and the delay time can be shortened without changing the write voltage.
よってその結果として、高速動作の高性能プログラマブ
ル集積回路が得られる。The result is therefore a high performance programmable integrated circuit with high speed operation.
【図面の簡単な説明】
第1図は本発明の半導体集積回路のプログラマブル素子
の断面図、第2図は従来例のプログラマブル素子の断面
図である。
1・・・・・・基板、2・・・・・・フィールド酸化膜
、3・・・・・N°型型数散層4・・・・・・凸部、5
・・・・・・プログラム用酸化膜、6・・・・・・上部
電極。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view of a programmable element of a semiconductor integrated circuit according to the present invention, and FIG. 2 is a sectional view of a conventional programmable element. DESCRIPTION OF SYMBOLS 1...Substrate, 2...Field oxide film, 3...N° type scattering layer 4...Protrusion, 5
... Programming oxide film, 6 ... Upper electrode.
Claims (1)
型半導体基板中に形成された前記基板よりも高不純物濃
度でかつ反対導電型の拡散層からなる下部電極と、前記
下部電極上に形成された絶縁膜と、前記絶縁膜上に形成
された上部電極とを備え、前記下部電極または前記上部
電極のうち陰極として用いる電極の前記絶縁膜と接する
面に凸部が形成されていることを特徴とする半導体集積
回路のプログラマブル素子。a lower electrode formed in a semiconductor substrate of one conductivity type divided into a plurality of regions by a thick isolation oxide layer, and comprising a diffusion layer having a higher impurity concentration than the substrate and of an opposite conductivity type; and a lower electrode formed on the lower electrode. and an upper electrode formed on the insulating film, and a convex portion is formed on a surface of the lower electrode or the upper electrode used as a cathode in contact with the insulating film. Characteristic programmable elements of semiconductor integrated circuits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2147848A JPH0442960A (en) | 1990-06-06 | 1990-06-06 | Programmable element of semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2147848A JPH0442960A (en) | 1990-06-06 | 1990-06-06 | Programmable element of semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0442960A true JPH0442960A (en) | 1992-02-13 |
Family
ID=15439626
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2147848A Pending JPH0442960A (en) | 1990-06-06 | 1990-06-06 | Programmable element of semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0442960A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006080550A1 (en) * | 2005-01-31 | 2006-08-03 | Semiconductor Energy Laboratory Co., Ltd. | Memory device and semiconductor device |
| JP2006237593A (en) * | 2005-01-31 | 2006-09-07 | Semiconductor Energy Lab Co Ltd | Memory device and semiconductor device |
-
1990
- 1990-06-06 JP JP2147848A patent/JPH0442960A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006080550A1 (en) * | 2005-01-31 | 2006-08-03 | Semiconductor Energy Laboratory Co., Ltd. | Memory device and semiconductor device |
| JP2006237593A (en) * | 2005-01-31 | 2006-09-07 | Semiconductor Energy Lab Co Ltd | Memory device and semiconductor device |
| US8023302B2 (en) | 2005-01-31 | 2011-09-20 | Semiconductor Energy Laboratory Co., Ltd. | Memory device and semiconductor device |
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