JPH0443070U - - Google Patents

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Publication number
JPH0443070U
JPH0443070U JP8499390U JP8499390U JPH0443070U JP H0443070 U JPH0443070 U JP H0443070U JP 8499390 U JP8499390 U JP 8499390U JP 8499390 U JP8499390 U JP 8499390U JP H0443070 U JPH0443070 U JP H0443070U
Authority
JP
Japan
Prior art keywords
clamp circuit
clamped signal
amplifier
input
clamp
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8499390U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8499390U priority Critical patent/JPH0443070U/ja
Publication of JPH0443070U publication Critical patent/JPH0443070U/ja
Pending legal-status Critical Current

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  • Picture Signal Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す回路図で第2
図はダイオードの順方向の電流特性を示す図、第
3図乃至第5図は従来の回路を説明するための図
である。 TR,TR,TR……トランジスタ、R
〜R……抵抗、C,C……コンデンサで
ある。
Figure 1 is a circuit diagram showing one embodiment of the present invention.
This figure shows the forward current characteristics of a diode, and FIGS. 3 to 5 are diagrams for explaining conventional circuits. TR 1 , TR 2 , TR 3 ...transistor, R
1 to R6 ...resistors, C1 , C2 ...capacitors.

補正 平2.11.1 図面の簡単な説明を次のように補正する。 明細書第6頁第6行目及至第7行目の「説明す
るための図である。」とあるを「説明するための
図、第6図は電圧レベルの変動を示す図である。
」と訂正する。
Amendment 2.11.1 The brief description of the drawing is amended as follows. In the 6th and 7th lines of page 6 of the specification, the phrase ``This is a diagram for explaining.'' has been replaced with ``Figure 6 is a diagram showing fluctuations in voltage level.
” he corrected.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] クランプレベル設定電圧と被クランプ信号を差
動アンプ入力とし、そのアンプ出力により電流ス
イツチ素子を制御するクランプ回路に於て、被ク
ランプ信号入力側トランジスタのコレクタを電源
に直結し飽和を防止したことを特徴とするクラン
プ回路。
In a clamp circuit in which the clamp level setting voltage and the clamped signal are input to a differential amplifier, and the current switch element is controlled by the output of the amplifier, saturation is prevented by directly connecting the collector of the transistor on the input side of the clamped signal to the power supply. Features a clamp circuit.
JP8499390U 1990-08-11 1990-08-11 Pending JPH0443070U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8499390U JPH0443070U (en) 1990-08-11 1990-08-11

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8499390U JPH0443070U (en) 1990-08-11 1990-08-11

Publications (1)

Publication Number Publication Date
JPH0443070U true JPH0443070U (en) 1992-04-13

Family

ID=31633850

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8499390U Pending JPH0443070U (en) 1990-08-11 1990-08-11

Country Status (1)

Country Link
JP (1) JPH0443070U (en)

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