JPH0443360B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit incorporating a read-only memory (hereinafter referred to as ROM) that stores parallel data with a number of bits greater than the number of bits of an internal data bus.

[Conventional technology]

The number of parallel output bits of the ROM in a single chip such as a microcomputer is the same as, or at most twice, the number of internal processing bits (the number of bits of the internal data bus), so during testing, the ROM is output via the internal data bus. The stored data was sequentially output from the I/O port to the outside for verification.

FIG. 2 is a circuit diagram of a conventional integrated circuit incorporating this type of ROM. During normal use,
The 4-bit parallel data of the ROM 21 is output to an internal data bus 22 (4 bits), latched to 4-bit output ports 28-32 by a control signal from an instruction decoder 23, and output to the outside of the integrated circuit. On the other hand, during testing, a test signal is input to the decoder 23 from the test signal input terminal 25, and the decoder 23 outputs the 4-bit parallel data from the ROM 21 to the internal data bus 22. This data is then latched into the 4-bit output port 28 and data verification is performed.

By the way, in recent years, the operating frequency of calculators and other devices has been lowered to reduce power consumption, and as a result,
The number of parallel output bits of ROM has become much larger than the number of internal processing bits. To verify the ROM data in such a case,
After the parallel data read from the ROM 21 is temporarily stored in the register 27, there is no choice but to divide it and sequentially output it to the output port 28.

For this reason, in the past, it took a lot of time to verify data, and if there was an output from the ROM 21 that did not enter the internal data bus 22, it was impossible to verify this type of data. Instead of the above method, a method can be considered in which the calculation section 24 executes calculations for verification and verification is performed from the calculation results, but this method takes more time than the above method, and it is impossible to use all the data. cannot be verified.

[Problem that the invention seeks to solve]

As mentioned above, conventional integrated circuits have a problem in that when the number of output bits of ROM data exceeds the number of internally processed bits, it takes a lot of time to verify the stored data.

An object of the present invention is to provide an integrated circuit that allows stored data to be verified easily and in a short time.

[Means for solving problems]

The integrated circuit of the present invention has a data bus that is separate from the internal data bus and has the number of bits equivalent to the parallel data of the ROM, and the parallel data of the ROM that is output to the data bus during testing is transferred to the internal data bus during normal use. and an output switching circuit that outputs data on the data bus to a common output terminal.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of one embodiment of an integrated circuit according to the present invention. ROM1 is a read-only memory that stores 20-bit parallel data.On the other hand, those 8-bit buses are connected to the instruction decoder 3, the 4-bit bus is connected to the internal data bus 2 (4 bits), and the 4-bit bus is connected to the internal data bus 2 (4 bits). At the same time as each signal is output to the register 7, the 20-bit bus 14 is output to an output switching circuit 13, which will be described later. The output switching circuit 13 is connected to the 20-bit parallel data output from the ROM 1 via the aforementioned data bus 14 and the output from the internal data bus 2 via five 4-bit buses. During normal use, the output switching circuit 13 outputs data from the internal data bus 2 onto the 4-bit output ports 8 to 12. On the other hand, during testing, a test signal is input from the test signal input terminal 5. Luxion decoder 3
opens the gates of all 4-bit output ports 8 to 12, and at the same time the switching circuit 13 opens the gates of all 4-bit output ports 8 to 12.
1 to all output ports 8-12 via the 20-bit bus 14.
output directly and simultaneously on top. Note that the calculation section 4 performs calculations via the instruction decoder 3, and the input port 6 inputs data via the internal data bus 2.

As described above, according to the integrated circuit according to this embodiment,
Since all the parallel data in the ROM 1 can be directly and simultaneously output to all the output ports 8 to 12, verification of a large amount of stored data can be performed extremely easily and in a short time. Incidentally, additional processing such as the output switching circuit 13 on a single chip can be easily performed due to recent advances in delicate processing technology.

〔Effect of the invention〕

As explained above, according to the integrated circuit according to the present invention, there is a connection between the internal data bus and the output port.
By providing an output switching circuit with a data bus that connects directly to the ROM without going through the internal data bus, all of the multi-bit parallel data stored in the ROM can be directly and simultaneously output to all output ports. Because it is composed of
This has the advantage that verification of a large amount of parallel data in the ROM can be performed extremely easily and in a short time.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of an integrated circuit according to the present invention, and FIG. 2 is a circuit diagram of a conventional example of an integrated circuit. 1...ROM, 2...internal data bus, 3...
Instruction decoder, 5...Test signal input terminal, 13...Output switching circuit, 14...20 bit bus.

Claims (1)

[Claims] 1. In an integrated circuit that has a built-in memory that stores parallel data with a number of bits greater than the number of bits of the internal data bus, a data bus having a number of bits equal to the number of bits of the parallel data is provided independently of the internal data bus, and the circuit is not normally used. Output switching that sometimes outputs data on the internal data bus from corresponding output terminals in predetermined basic units, while during testing, parallel data in the memory is output simultaneously from the output terminals using the data bus. An integrated circuit characterized by having a circuit.