JPH0443452B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data converter for protecting data from errors and tampering in data communications.

(Prior art and its problems) In packet data communication, when an error is detected in a packet on the receiving side, there are many systems in which the packet is discarded and a retransmission request is issued. In this case error detection codes are used. By the way, it has been known that when encryption is used, data can be protected from tampering by a third party by performing error detection encoding before encryption. However, even in combination with cryptography, error detection encoding is not as simple as without cryptography.

(Object of the invention) An object of the invention is to provide a data converter that eliminates the above-mentioned drawbacks.

(Structure of the Invention) The data converter of the present invention includes a first data conversion circuit and a second data conversion circuit. The first data conversion circuit includes a storage means for storing a digital pattern, a pattern conversion means for outputting a digit depending on the digital pattern, and an M (M is adding means for calculating a sum modulo a positive integer); and adding at least one digit of the digital pattern stored in the storage means as the sum modulo M of the data digit and one or more digits of the digital pattern. and rewriting means for rewriting at least one digit of the digital pattern into a sum modulo M of at least two digits of the digital pattern, and the sum outputted by the adding means is used as output data. It is characterized by

Further, the second data conversion circuit is a data converter for converting data digits, and includes a storage means for storing a digital pattern, a pattern conversion means for outputting a digit depending on the digital pattern, and a data converter for converting the data digits and the data digits. addition means for calculating the sum modulo M (M is a positive integer) of the digits output by the pattern conversion means; rewriting means for rewriting at least one digit of the digital pattern into a sum modulo M of at least two digits of the digital pattern; It is characterized in that the sum outputted by the adding means is used as output data.

(Operation and principle of the present invention) FIG. 4 is a diagram showing the operation and principle of the present invention. In the figure, on the transmitting side, a packet sent from an information source 401 is appended with a specific pattern at the end by a pattern adding circuit 402, encrypted by an encoder 403, and sent out.

On the receiving side, the packet sent from the transmitting side is decoded by a decoder 404, and then sent to a pattern detection circuit 405.
It is determined whether the pattern is added to the end of the packet or not. If it is added, it is determined that there is no error or tampering, and if the pattern has changed to a different pattern, it is determined that there is an error or tampering, and the receiving purpose 406 is determined. Send a packet. Here, the encoder 403 and the decoder 4
04 is an encoder in which when a bit error occurs on the transmission path, the error propagates to the end of the packet,
In the case of a decoder, errors during transmission or tampering by a third party affect the specific pattern at the end of the packet, causing the specific pattern to change. Therefore, errors or tampering can be detected. Examples of encoders and decoders that propagate errors will be shown in the embodiments.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of a first data conversion circuit according to the present invention. To make the explanation easier to understand, it is assumed that all data are expressed in binary. In the figure, shift register 10
1 stores a bit pattern representing the internal state, and stores the initial pattern in the initial state. The shift register has a feedback section from the topmost register. An example of the wiring structure of the feedback section is the wiring used in an M-sequence generator. The code conversion circuit 102 converts the bit pattern representing the internal state stored in the register series 101 and outputs one bit.
The exclusive OR element 103 performs an exclusive OR operation on the output and the input bit, and uses the result as an output bit. The output bit is exclusive-ORed (EOR)ed with the bit from the most significant register of the shift register 101 and input to the least significant register of the shift register. Thus, the internal state changes.

FIG. 2 is a block diagram showing an embodiment of a second data conversion circuit according to the present invention. As in the first embodiment of the data conversion circuit, the discussion will proceed assuming that the data is binary data. Shift register 201 has a feedback section and is the same as 101, but the bit input to the lowest register is the exclusive OR of the bit from the highest register and the input bit to the device of the present invention. Other parts are the same as in FIG.

One of the first data conversion circuit embodiment and the second data conversion circuit embodiment is used for encryption, and the other is used for decryption. At this time, the reason that errors in transmission are spread by decoding is that these errors are trapped in the shift register and cannot be removed. If the same initial pattern is set in shift registers 101 and 201, if there are no errors, after decoding,
The original binary data is created when the internal state is
If they match, the output bits of the code conversion circuit will be the same, and after decoding, the same bits will be added twice modulo 2 to the data bits before encryption, so the original state will be restored. shift register 101,
Since the same bit is stored in the lowest register of 201, the contents of the shift registers match.
If an error occurs during transmission, the data will not match after decoding. In this case, if the packet is retransmitted and the initial pattern is matched at the beginning of the packet, the error will be removed by retransmission. The initial pattern can be a key. The code conversion circuit can be constructed from an encoder and memory such as ROM or RAM, but it can also be constructed from the circuit shown in FIG. In FIG. 3, the shift register 101 or 201 is shown as 331.
It is shown with a number. 351 is connected to exclusive OR element 103 or 203,
352 corresponds to 104 or 204.

In the figure, 331 is a 67-stage shift register, into which an initial pattern is entered at the time of initial setting. 30
1 to 321 are circuits shown in FIG. 3b consisting of a ROM and a selector. The ROM 341 is a 16×8 bit ROM, and in response to 4 bits of address input, outputs 8 bits stored at the address. The selector 342 determines which bit to select among the 8 bits based on a portion (3 bits) of the key pattern input from the input terminal 343, and outputs the 1 bit thus determined.

Note that the input terminal 343 is omitted in FIG. 3a to avoid complexity. 321 is 16 x 1 bit
It is ROM. The key pattern consists of 60 bits, and each 3 bits are input into 301-320.
The patterns 301 to 321 stored in the ROM are random patterns, for example physical random patterns. This pattern can also be used as a key.

In the above embodiment, the shift register is
Can be configured with RAM, and ROM is also non-volatile
It can be used as RAM. Also, 3 in Figure 3a
All 01 to 321 are 16×1 bit ROM,
An initial pattern can also be used as a key. All these modifications are included within the scope of this invention.

(Effects of the Invention) As explained in detail above, by using the present invention, the sending side does not have to perform calculations for error detection encoding such as "creation of ECC", but can simply identify the message immediately after sending the message. By adding a pattern (any pattern can be used) and by inspecting this specific pattern, the receiving side can detect errors or falsification of data, and its use in data communication has a great effect on performance. .

[Brief explanation of the drawing]

1 and 2 are block diagrams showing an embodiment of a first data conversion circuit and a second embodiment of the data conversion circuit of the present invention, and FIGS. 3a and 3 are block diagrams showing a code conversion circuit, FIG. 4 is a block diagram showing the operating principle of the present invention. In the figure, 101, 201, 331 are shift registers, 102, 202 are code conversion circuits, 10
3,203,332 is an exclusive OR element, 32
1,341 is ROM, 342 is selector, 401
402 is an information source, 402 is a pattern addition circuit, 403 is an encoder, 404 is a decoder, 405 is a pattern detection circuit, and 406 is a reception purpose.

Claims (1)

[Scope of Claims] 1. A data converter comprising an encryption device that converts data digits to generate encrypted data, and a decryption device that converts the encrypted data and decrypts the data digits, comprising: (1) a digital a memory means for memorizing the pattern;
a pattern conversion means for outputting a digit depending on the digital pattern; a sum modulo M (M is a positive integer) of the data digit and the digit output from the pattern conversion means; the sum is determined as output data; an adding means, and rewriting at least one digit of the digital pattern stored in the storage means into a sum modulo M of the digit outputted by the adding means and one or more digits of the digital pattern; (2) a first data conversion circuit comprising: rewriting means for rewriting at least one digit of the pattern into a sum modulo M of at least two digits of the digital pattern; (2) storage means for storing the digital pattern;
a pattern conversion means for outputting a digit depending on the digital pattern; a sum modulo M (M is a positive integer) of the data digit and the digit output from the pattern conversion means; the sum is determined as output data; rewriting at least one digit of the digital pattern stored by the adding means and the storage means into a sum modulo M of the data digit and one or more digits of the digital pattern;
At least one digit of the digital pattern is combined with at least two digits of the digital pattern.
and a second data conversion circuit comprising rewriting means for rewriting two digits into a sum modulo M, and one of the first data conversion circuit and the second conversion circuit is used as the encryption device. , the other as the decoding device.