JPH0443453B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data converter for protecting data from errors and tampering in data communications.

(Prior art and its problems) In packet data communication, when an error is detected in a packet on the receiving side, there are many systems in which the packet is discarded and a retransmission request is issued. In this case error detection codes are used. By the way, it has been known that when encryption is used, data can be protected from tampering by a third party by performing error detection encoding before encryption. However, even in combination with encryption, error detection encoding is not as simple as without encryption.

(Object of the invention) An object of the invention is to provide a data converter that eliminates the above-mentioned drawbacks.

(Structure of the Invention) The data converter of the present invention includes a first data conversion circuit and a second data conversion circuit. The first data conversion circuit includes a storage means for storing a digital pattern, a pattern conversion means for outputting at least two digits depending on the digital pattern, and a data digit and at least one output from the pattern conversion means. addition means for calculating the sum modulo M (M is a positive integer) of digits; at least one digit of the digital pattern stored in the storage means; Rewrite one digit and one or more digits of the digital pattern as the sum modulo M, and rewrite at least one digit of the digital pattern as the sum modulo M of at least two digits of the digital pattern. and a rewriting means for rewriting the adding means, and the sum outputted from the adding means is used as output data.

The second data conversion circuit is a data converter for converting data digits, and includes a storage means for storing a digital pattern, a pattern conversion means for outputting at least two digits depending on the digital pattern, and a data converter for converting the data digits. and an addition means for calculating the sum modulo M (M is a positive integer) of at least one digit outputted by the pattern conversion means; The output digit, at least one digit output from the pattern conversion means, and one or more digits of the digital pattern are rewritten into a sum modulo M, and at least one digit of the digital pattern is converted into the digital pattern. and rewriting means for rewriting at least two digits of digits into a sum modulo M, and the sum output from the adding means is used as output data.

(Operation and principle of the present invention) FIG. 5 is a diagram showing the operation and principle of the present invention. In the figure, on the transmitting side, a packet sent from an information source 501 is appended with a specific pattern at the end by a pattern adding circuit 502, encrypted by an encoder 503, and sent out.

On the receiving side, the packet sent from the transmitting side is decoded by a decoder 504, and then sent to a pattern detection circuit 505.
It is determined whether or not the pattern is added to the end of the packet. If it is added, it is determined that there is no error or tampering, and if the pattern has changed to a different pattern, it is determined that there is an error or tampering, and the receiving purpose 506 is determined. Send a packet. Here, the encoder 503 and the decoder 5
04 is an encoder in which when a bit error occurs on the transmission path, the error propagates to the end of the packet,
In the case of a decoder, errors during transmission or tampering by a third party affect the specific pattern at the end of the packet, causing the specific pattern to change. Therefore, errors or tampering can be detected. Examples of encoders and decoders that propagate errors will be shown in the embodiments.

(Embodiment) FIG. 1 is a block diagram showing a first embodiment of a first data conversion circuit according to the present invention. In order to make the explanation easier to understand, it is assumed that all data are expressed in bilinas. In the figure, a shift register 101 stores a bit pattern representing an internal state, and stores an initial pattern in an initial state. The shift register has a feedback section from the topmost register. An example of the wiring structure of the feedback section is the wiring used in an M-sequence generator. Code conversion circuit 102
converts the bit pattern representing the internal state stored in the register series 101 and outputs 2 bits. The exclusive OR element 103 performs an exclusive OR operation on one of the outputs and the input bit, and uses the result as an output bit. The output bits are the remaining bits output from the code conversion circuit 102 and the shift register 10.
Exclusive OR (EOR) from the topmost register of 1
is taken and input to the lowest register of the shift register. Thus, the internal state changes.

FIG. 2 is a block diagram showing a first embodiment of the second data conversion circuit according to the present invention. As in the first embodiment of the first data conversion circuit, the discussion will proceed assuming that the data is binary data. shift register 20
1 has a feedback section and is the same as 101, but the bit input to the lowest register is an exclusive logic of the bit from the highest register, the input bit to the device of the present invention, and the output of the code conversion circuit 202. It is Japanese. Other parts are the same as in FIG.

One of the first embodiment of the first data conversion circuit and the first embodiment of the second data conversion circuit is used for encryption, and the other is used for decryption. At this time, the reason that errors in transmission are spread by decoding is that these errors are trapped in the shift register and cannot be removed. If the same initial pattern is set in shift registers 101 and 201, if there are no errors, the original binary data will be returned after decoding.If the internal states match, the output bits of the code conversion circuit will become the original binary data. This is because the bits become the same, and after decryption, the same bit is added twice modulo 2 to the data bits before encryption, so the data returns to the original state. Since the same bits are stored in the lowest registers of shift registers 101 and 201, the contents of the shift registers are the same. If an error occurs during transmission, the data will not match after decoding. In this case, if the packet is retransmitted and the initial pattern is matched at the beginning of the packet, the error will be removed by retransmission. The code conversion circuit can be constructed from a commercially available encoder.

FIG. 3a is a block diagram showing a second embodiment of the first conversion circuit according to the present invention. In the figure,
331 is a 67-stage shift register, and an initial pattern is stored at the time of initial setting. 301 to 322 are
The circuit shown in FIG. 3b consists of a ROM and a selector. The ROM 341 is a 16×8 bit ROM, and in response to 4 bits of address input, outputs 8 bits stored at the address. The selector 342 determines which bit to select among the 8 bits based on a portion (3 bits) of the key pattern input from the input terminal 343, and outputs the 1 bit thus determined.

Note that the input terminal 343 is omitted in FIG. 3a to avoid complexity. 321,322 is 16×
It is a 1-bit ROM. The key pattern consists of 60 bits, and each 3 bits are input into 301-320. The output of the ROM 321 is EORed with the input bit from the input terminal 353 and output from the output terminal 3.
54. The output of the ROM 322 is EORed with the output of the exclusive OR element 351 at 352 and fed back, and the most significant bit of the shift register 331 is subjected to exclusive OR (EOR) with the exclusive OR element 332. It is input to the least significant bit of 331. Exclusive OR element 35
Outputs from the ROM 321 are output once every eight times to the ROM 321. That is, the shift register shifts eight times as fast as the data bits to be encoded.
Therefore, only 351 operates with a 1/8th clock. This number 8 is just one example, and it may be 1. The patterns 301 to 322 stored in the ROM are random patterns, for example physical random patterns. This pattern can also be used as a key.

In Figure 3a, the input terminal is changed to 354, the output terminal is changed to 353, the inputs of exclusive OR element 351 are the output bit of 321 and the bit from 354, and the output of 351 is changed to output to 353. This results in a second embodiment of the second data conversion circuit. It is clear that the second embodiment of the first conversion circuit and the second embodiment of the second conversion circuit are opposite circuits to each other.

FIG. 4 shows the third conversion circuit of the first conversion circuit according to the present invention.
FIG. 2 is a configuration diagram showing an example. 431 is a 67-stage shift register, 401 to 420 are 32 x 1 bit ROM, and 421 and 422 are 16 x 1 bit ROM.
It is a ROM. The most significant bit of the 5-bit address input for each ROM from 401 to 420 is 1 bit of the key pattern. The remaining 4 bits are connected to the output of the shift register 431 or ROM using the third
Same as figure a. However, among the inputs to ROM422, 3 bits are the 3 bits of the key pattern.
The EOR of the outputs of ROMs 417, 418, and 419 is used. The 3 bits of this key pattern k ₀ ′, k ₁ ′,
k ₂ ', and the inputs from key patterns 401 to 420 are k ₀ , k ₁ , . . . , k ₁₉ , respectively. The key pattern consists of 64 bits as a whole, which are arranged into 8 words of 8 bits each. FIG. 6 shows a diagram in which key patterns are arranged. In this embodiment, as in the second embodiment of the first conversion circuit, 1-bit data conversion is performed in 8 clocks. k ₀ ′, k ₁ ′,
k ₂ ′, k ₀ , k ₁ , . . . , k ₁₉ are bits at the positions shown in FIG. Now, each time the clock advances, the key word is cyclically shifted word by word. That is, the sixth
Move the top row of the diagram to the bottom row and move the other rows up one place. Therefore, it returns to the original state in 8 clocks. At this time, k ₀ ′, k ₁ ′, k ₂ ′, k ₀ , k ₁ , ..., k ₁₉ are always at the same relative position. That is _{, the} bits _at the positions _shown in _{FIG .}
used as For other connections, see Figure 3a.
is the same as

Just as the second embodiment of the second conversion circuit was created from the second embodiment of the first conversion circuit, the third embodiment of the second conversion circuit was created from the third example of the first conversion circuit. It is clear that the circuits are opposite to each other.

In the above embodiment, the shift register is
It can be configured with RAM, and ROM can also be a nonvolatile memory. Furthermore ROM401
420 can be made all or part of them common to save ROM. Also, the third
All 301 to 322 in figure a are 16×1 bit
It can be a ROM and the initial pattern of the shift register can be used as a key. All of these are included within the scope of the present invention.

(Effects of the Invention) As explained in detail above, by using the present invention, the sending side does not have to perform calculations for error detection encoding such as "creation of ECC", but can simply identify the message immediately after sending the message. The receiving side can detect errors or falsification of data simply by checking this specific pattern, and its use in data communication has a great effect on performance. .

[Brief explanation of the drawing]

1, 2, 3a, b, and 4 are a first embodiment of the first data conversion circuit, a first embodiment of the second data conversion circuit, and a first embodiment of the present invention. A block diagram showing a second embodiment of the data conversion circuit and a third embodiment of the first data conversion circuit, FIG. 5 is a diagram showing the operating principle of the present invention, and FIG. 6 is a pattern diagram showing key patterns. It is. In the figure, 101, 201, 331, 431
is a shift register, 102, 202 is a code conversion circuit, 103, 104, 203, 204, 351,
352, 332, 432, 433434, 43
5,451,452 is an exclusive OR element, 32
1,322,341,401-422 are ROM,
342 is a selector, 501 is an information source, 502 is a pattern addition circuit, 503 is an encoder, 504 is a decoder, 505 is a pattern detection circuit, and 506 is a receiving purpose.

Claims (1)

[Scope of Claims] 1. A data converter comprising an encryption device that converts data digits to generate encrypted data, and a decryption device that converts the encrypted data and decrypts the data digits, comprising: (1) a digital a memory means for memorizing the pattern;
pattern converting means for outputting at least two digits depending on the digital pattern; and calculating the sum modulo M (M is a positive integer) of the data digit and at least one digit output from the pattern converting means. addition means for outputting a sum as output data; at least one digit of a digital pattern stored in the storage means; at least one digit output from the addition means; at least one digit output from the pattern conversion means; and one of the digital patterns. or a first rewriting means for rewriting at least one digit of the digital pattern into a sum modulo M of at least two digits of the digital pattern; a data conversion circuit; (2) storage means for storing digital patterns;
pattern converting means for outputting at least two digits depending on the digital pattern; and calculating the sum modulo M (M is a positive integer) of the data digit and at least one digit output from the pattern converting means. addition means for outputting a sum as output data; at least one digit of a digital pattern stored in the storage means; at least one digit outputted by the pattern conversion means; and one or more of the digital patterns. a second data conversion circuit comprising: rewriting means for rewriting at least one digit of the digital pattern into a sum modulo M of at least two digits of the digital pattern; A data converter comprising: one of the first data conversion circuit and the second conversion circuit being used as the encryption device and the other being used as the decryption device.