JPH044345U - - Google Patents
Info
- Publication number
- JPH044345U JPH044345U JP4354190U JP4354190U JPH044345U JP H044345 U JPH044345 U JP H044345U JP 4354190 U JP4354190 U JP 4354190U JP 4354190 U JP4354190 U JP 4354190U JP H044345 U JPH044345 U JP H044345U
- Authority
- JP
- Japan
- Prior art keywords
- bank
- switching
- control circuit
- lock signal
- execution
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Description
第１図は本考案の一実施例の回路ブロツク図、
第２図ａ，ｂは実施例のバンク切換えの際の命令
の例と、その実行フローを示す図、第３図は実施
例のメモリ空間と、各バンクとの切換関係を示す
図、第４図は従来例のメモリ空間と各バンク切換
関係を示す図である。
１…ＣＰＵ、４…バンクレジスタ、５…バンク
切換回路、６〜６Ｎ…バンクメモリ。
FIG. 1 is a circuit block diagram of an embodiment of the present invention.
FIGS. 2a and 2b are diagrams showing examples of instructions and their execution flows when switching banks in the embodiment; FIG. 3 is a diagram showing the memory space in the embodiment and the switching relationship with each bank; and FIG. The figure is a diagram showing the memory space and each bank switching relationship in a conventional example. 1...CPU, 4...Bank register, 5...Bank switching circuit, 6-6N...Bank memory.
Claims (1)
共用する方式のメモリバンク制御回路において、 ＣＰＵからのバンク切換指令によつて、切換先
のバンクを選択してセツトしておくバンクレジス
タと、入力するバスロツク信号がアクテイブにな
つたときに、前記の設定バンクを選択するバンク
切換回路とを備え、ＣＰＵがジヤンプ命令、コー
ル命令、リターン命令等をフエツチしたときに、
実行として前記バスロツク信号をアクテイブとな
し、切換先のバンクの所定のアドレスに実行アド
レスを移らせることを特徴とするメモリバンク制
御回路。[Claim for Utility Model Registration] In a memory bank control circuit in which a plurality of bank memories share the same memory space area, a bank to which switching is to be selected is selected and set in response to a bank switching command from a CPU. and a bank switching circuit that selects the set bank when the input bus lock signal becomes active, and when the CPU fetches a jump instruction, call instruction, return instruction, etc.
A memory bank control circuit characterized in that, as an execution, the bus lock signal is made active and the execution address is moved to a predetermined address of a switching destination bank.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4354190U JPH044345U (en) | 1990-04-25 | 1990-04-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4354190U JPH044345U (en) | 1990-04-25 | 1990-04-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH044345U true JPH044345U (en) | 1992-01-16 |
Family
ID=31556040
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4354190U Pending JPH044345U (en) | 1990-04-25 | 1990-04-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH044345U (en) |
-
1990
- 1990-04-25 JP JP4354190U patent/JPH044345U/ja active Pending
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