JPH0443589B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention is applicable to characters generated under the control of a CPU, etc.
It relates to an image display device that outputs information such as graphic figures to a display device such as a CRT.
In particular, the present invention relates to an image display device that divides a display screen into a plurality of screens and displays images.

[Conventional technology]

An example of an image display device that divides a display screen into a plurality of screens and displays them is disclosed in Japanese Patent Laid-Open No. 58-35592. FIG. 4 is a block connection diagram showing such an image display device, and in the figure, 1
a, 1b, 1c are image memories, 2 is a vertical division position specification register, 3 is a horizontal division position specification register,
4 is a vertical scanning position counter, 5 is a horizontal scanning position counter, 6 is a vertical position detection circuit, 7 is a horizontal position detection circuit, and 8 is a selection circuit.

In such an image display device, a vertical scanning counter 4
The vertical position detection circuit 6 compares the outputs of the horizontal scanning counter 5 and the horizontal division position designation register 2 to detect the vertical position of the screen.
The selection circuit 8 operates to select and output one of the image memories 1a to 1c in accordance with these detection outputs.

[Problem that the invention seeks to solve]

Since the conventional image display device is configured as described above, the screen is divided by the division position designation registers 2 and 3, the scanning position counters 4 and 5, and the position detection circuits 6 and 7, and the screen division pattern is changed. When attempting to do so, the contents of split position specification registers 2 and 3 must be rewritten, and the data of the original screen split pattern is changed to a new screen split pattern without any modification. was impossible.

This invention was made to solve the above-mentioned problems, and it is an object of the present invention to provide an image display device that can easily change to a new screen division pattern without making any changes to the original screen division pattern data. purpose.

[Means for solving problems]

The image display device according to the present invention stores characters, graphic figures, etc. in a plurality of image memories, sets display priorities for each of the image memories by a priority setting section, and sets the display priority for each of the image memories. A gate is applied in the priority data control section, and according to the output of the priority data control section, from among the plurality of image memories,
By selecting data in one image memory using a data selection section, one display screen can be divided into a plurality of screens for display.

[Effect]

The image display device according to the present invention prioritizes data valid signals output from a plurality of image memories and uses this as a data selection signal, and also provides a signal independent of priority setting data for this data selection signal. Split screen display is achieved by using the gate signal as a control signal and selectively outputting only specific image data.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 11a to 11c are image memories, and 21a to 21c are image memories 11a to 11c.
Image data, 22a to 22c, respectively output by
is the same data valid signal, 12 is the image memory 11
a priority setting unit that sets priorities for the image data 21a to 21c and data valid signals 22a to 22c of a to 11c; 13, a priority data control unit that gates the output of the priority setting unit 12;
3a to 23c are gate signals for gating the output of the priority setting section 12 in the priority data control section 13;
This is a data selection section that selects one of the image data 21a to 21c based on the data valid signals 22a to 22c that have passed through the image data 21a to 21c.

Further, FIG. 2 is an internal block diagram of the priority data control section 13 and data selection section 14 shown in FIG. 1, and FIG. 3 is an example of divided display performed using the present invention.

In Fig. 3, image (A) is image memory 11a, image (B) is image memory 11b, and image (C) is image memory 1.
The explanation will be continued from now on by making it correspond to 1c. in this case,
The data valid signal 22a of the image memory 11a is "1" only in the region (A), and the data valid signal 22b of the image memory 11b is "1" only in the region (B) (including the part overlapping with the region (A)). The data valid signal 22c of the image memory 11c is "1" in the area (C), that is, in the entire area.

Outputs 21a-21 of image memories 11a-11c
The priorities of the components c and 22a to 22c are set in the priority setting section 12 under the control of a CPU (not included in this figure) or the like. In the case of Figure 3, the image
The priority order of (A), (B), and (C) is (A)>(B)>(C), so the outputs 21a and 2 of the image memory 11a
The highest priority is set to 2a, the next highest priority is set to outputs 21b and 22b of the image memory 11b, and the lowest priority is set to outputs 21c and 22c of the image memory 11c. In this state, first consider the case of split display using pattern 3A shown in FIG.
are all set to "1". Next, consider the case where the divided pattern is changed from pattern 3A to pattern 3B. In this case, the gate signal for image (B) is "0", and the gate signals for image (A) and image (C) are "1". are set respectively. The operation at this time will be explained in more detail with reference to FIG. Paying attention to the lines on the screen indicated by l and m in FIG. 3, in the case of pattern 3A, in the sections [a, b] and [e, f], the data valid signal with the lowest priority is Only 52c is 1
and a data valid signal 52 with other priorities.
a, 52b are 0. In addition, the gate signal 23a
~23c are all “1”, so AND gate 4
1 and 42 become "0", and 43 becomes "1". Therefore, the outputs of the inverters 37 and 38 become "1", the output of the AND gate 35 becomes "0", and the output of the AND gate 36 becomes "1". As a result, AND
Among gates 31 to 33, only gate 33 is open, and the output of OR gate 34 is
The image data 51c having the lowest priority having passed through the AND gate 33, that is, the image data 21c in the image memory 11c is output.

In interval [b, c], the data valid signal 52b with the second highest priority and the data valid signal 52c with the lowest priority are "1", and the data valid signal with the highest priority is "1". 52a is "0". In addition, gate signals 23a to 23c
are all 1, so the AND gate 41 is "0",
AND gates 42 and 43 become "1". Therefore, the output of the inverter 37 becomes "1", the output of the inverter 38 becomes "0", the output of the AND gate 35 becomes "1", and the output of the AND gate 36 becomes "0". As a result, only the AND gate 32 is open among the AND gates 31 to 33, and the output of the OR gate 34 is connected to the AND gate 32.
The image data 51b having the second highest priority, that is, the image data 21b in the image memory 11b, is output.

In interval [c, d], all data valid signals 52a to 52c are "1", and all gate signals 23a to 23c are also "1", so
The outputs of AND gates 41 to 43 are all "1". Therefore, the outputs of the inverters 37 and 38 are both "0", and the outputs of the AND gates 35 and 36 are also both "0". As a result, AND
Which gate is open among gates 31 to 33?
Only the AND gate 31 is used, and the OR gate 34 outputs the image data 51a having the highest priority that has passed through the AND gate 31, that is, the image data 21a of the image memory 11a.

In interval [d, e], the data valid signal 52a with the highest priority and the data valid signal 52c with the lowest priority are "1", and the data valid signal with the second priority is "1". 52b is "0". In addition, gate signals 23a to 23c
are all "1", so AND gates 41, 4
The output of the gate 3 becomes "1" and the output of the AND gate 42 becomes "0". Therefore, the outputs of the inverters 37 and 38 are "0" at 37 and "1" at 38, and the outputs of the AND gates 35 and 36 are both "0". As a result, only the AND gate 31 is open among the AND gates 31 to 33, and the output of the OR gate 34 contains the image data 51a having passed through the AND gate 31 and having the highest priority, i.e. , the image data 21a of the image memory 11a is output.

As described above, the image memory 11c is stored in the sections [a, b] and [e, f], the image memory 11b is stored in the section [b, c], and the image memory 11 is stored in the section [c, e].
The image data of a is output, and as a result, a division pattern shown by pattern 3A is obtained.

Next, the case of pattern 3B will be explained in a similar manner.

In the sections [g, h], [k, p], only the data valid signal 52c with the lowest priority is "1", and the data valid signals 52a, 52b with other priorities are "0". be. Furthermore, since the gate signals 23a and 23c are "1" and the gate signal 23b is "0", the AND gate 41,
42 becomes "0" and AND gate 43 becomes "1".
Therefore, the outputs of the inverters 37 and 38 are "1", and the output of the AND gate 35 is "0",
AND gate 36 becomes "1". As a result,
Among the AND gates 31 to 33, only the AND gate 33 is open, and the OR gate 3 is open.
The image data 51c having the lowest priority having passed through the AND gate 33, that is, the image data 21c of the image memory 11c is outputted to the output of No. 4.

In interval [h, i], the data valid signal 52b with the second highest priority and the data valid signal 52c with the lowest priority are "1", and the data valid signal with the highest priority is "1". 52a is "0". In addition, gate signals 23a, 23c
is "1" and the gate signal 23b is "0", so the AND gates 41 and 42 are "0" and the AND gate 43 is "1". Therefore, the outputs of the inverters 37 and 38 become "1", the output of the AND gate 35 becomes "0", and the output of the AND gate 36 becomes "1". As a result, AND gates 31 to 33
The one that opens the gate is AND gate 33.
The OR gate 34 outputs the image data 51c having the lowest priority that has passed through the AND gate 33, that is, the image data 21c of the image memory 11c.

In interval [i, j], all data valid signals 52a to 52c are "1", gate signals 23a and 23c are "1", and gate signal 23b is "0", so AND gate 41,
43 is "1" and AND gate 42 is "0". Therefore, the inverter 37 output is "0",
The output of the inverter 38 becomes "1", and the outputs of the AND gates 35 and 36 both become "0". As a result, only AND gate 31 is open among AND gates 31 to 33, and OR gate 31 is open.
The output of the gate 34 includes the image data 51a having the highest priority that has passed through the AND gate 31.
That is, the image data 21a of the image memory 11a
is output.

In interval [j, k], the data valid signal 52a with the highest priority and the data valid signal 52c with the lowest priority are "1", and the data valid signal with the second priority is "1". 52b is "0". In addition, gate signals 23a, 23c
is "1" and the gate signal 23b is "0", so the AND gates 41 and 43 are "1", AND
Gate 42 becomes "0". Therefore, the output of the inverter 37 is "0", the output of the inverter 38 is "1", and the outputs of the AND gates 35 and 36 are both "0". As a result, AND gate 31
Only the AND gate 31 among the gates 33 to 33 is open, and the output of the OR gate 34 is as follows.
The image data 51a having the highest priority having passed through the AND gate 31, that is, the image data 21a of the image memory 11a is output.

As described above, the image data 21c of the image memory 11c is stored in the sections [g, i] and [k, p], and the image data 21c of the image memory 11a is stored in the section [i, k].
1a is output, and as a result, a divided pattern shown as pattern 3B is obtained.

As we have seen above, division patterns 3A to 3
The change to B can be made only by setting the gate signal 23b to "0" without requiring a change in priority, and therefore the change is reversed, i.e. from pattern 3B to pattern 3A. Returning can also be easily performed by setting the gate signal 23b to "1".

Note that although the above embodiment shows the case of three image memories, the number of image memories is not limited to this, and the circuit configuration shown in FIG. 2 is only one example, and is not limited to this. It's not something you can do. Further, the image data itself may be used as the data valid signal, and in this case, a superimposed screen of a plurality of screens is obtained.

〔Effect of the invention〕

As described above, according to the present invention, a data valid signal is output from an image memory, a priority is given to this signal and used as a data selection signal, and a gate is provided for the data valid signal independent of the priority setting. Since the gate is configured to be gated by a signal, the screen division pattern can be easily changed without making any changes to the priority settings.

[Brief explanation of drawings]

FIG. 1 is a block connection diagram of an image display device according to an embodiment of the present invention, FIG. 2 is a more detailed block connection diagram of the priority data control section and data selection section in FIG. 1, and FIG. FIG. 4 is a block connection diagram of a conventional image display device. 11a to 11c are image memories, 12 is a priority setting section, 13 is a priority data control section, 14 is a data selection section, 21a to 21c are image data, 22
a to 22c are data valid signals, and 23a to 23c are gate signals.

Claims (1)

[Claims] 1. In an image display device that outputs information such as characters, graphic figures, etc. generated under the control of a CPU, etc. to a display device such as a CRT, a plurality of image memories storing the above-mentioned characters, graphic figures, etc.;
a priority setting section that sets a display priority for each image memory, and a priority data control section that applies a gate to the output of the priority setting section for setting screen division positions. and a data selection section that selects and outputs one image memory data from among the plurality of image memory data according to the output of the priority data control section.