JPH0570158B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a display device equipped with an image memory, and more particularly to a device that combines a plurality of screens and displays them on one screen.

[Conventional technology]

With advances in digital image processing technology, so-called window technology has been developed that combines multiple screens and displays them on one screen.

These technologies include one memory for storing the main screen and another memory for storing the sub-screen to be combined with the main screen, and a comparison circuit and a condition judgment circuit are used to compare the addresses of both memories. There is a technique for synthesizing and displaying screens by switching them (Japanese Patent Laid-Open No. 160983/1983).

[Problem to be solved by the invention]

With the development of image processing technology, and depending on the processing status of an information processing device, it has become necessary to synthesize multiple screens. However, when trying to synthesize a number of screens, it is not possible to display three or more window displays in a multiplex manner unless it is determined which sub-screen should be displayed with priority. Furthermore, if such window display is controlled by software, it is necessary to calculate the overlapping sub-screens and write them to memory, which slows down the processing speed and makes it impossible to meet the demands of real-time processing. There is also the problem that an expensive dedicated processor is required.

An object of the present invention is to provide a display device that can display multiple windows at high speed with simple hardware.

[Means to solve the problem]

The present invention includes at least three memory modules, a display address generation circuit that updates a display address at regular intervals, and a memory module that stores address information that specifies an arbitrary rectangular area of a two-dimensional image stored in the memory module. a memory area register to
A display area register stores address information specifying a position on the display screen where the rectangular area is to be displayed, and the contents of the display area register and the display address are compared, and the display address is indicated by the contents of the display area register. a display area detection circuit that generates a display request signal indicating whether or not the area is included in the area indicated by the content of the memory area register; and a display area detection circuit that updates a memory address included in the area indicated by the contents of the memory area register when the display request signal is activated. and an address generation circuit that outputs the display request signals to the memory module according to the at least three display request signals corresponding to each memory module and a predetermined priority order. The present invention is characterized in that one of the display data accessed and output from each of the memory modules is selected. Furthermore, a circuit for dynamically changing the priority order may be added, or new display data may be obtained by calculating the display data with a fixed pattern prepared in advance or display data of another memory module. .

〔Example〕

Next, one embodiment of the present invention will be described with reference to the drawings. Figure 1 is a block diagram showing one embodiment of the present invention, and Figure 2 is "image cutting and pasting processing".
FIG. In this embodiment, three sets of image memory modules are provided, and three screens corresponding to each image memory module are
Let us take as an example the case of performing "paste" processing.

In FIG. 1, 1 to 3 are memory modules, 4 to 6 are address generation circuits that generate memory addresses 105 to 107 input to each memory module, and 7 is memory data output from each memory module. 1 out of 102-104
a multiplexer that selects one data and outputs it to a display (CRT) as display data 100;
9 and 10 are display area detection circuits that detect whether the current display address is included in the display areas of memory modules 2 and 3, respectively; 8 is a preset priority order that inputs display request signals 108 and 109; 11 is a display clock generation circuit, 12 and 13 are data area start address registers, and 14 and 15 are display area start address registers.
Registers 16 and 17 are data area final address registers, 18 and 19 are display area final address registers, and 110 is a display clock.

Note that the memory modules 1 to 3 use well-known two-port memories, which can be read and written from the outside, but the connections with the outside are omitted in FIG.

First, initial settings will be described with reference to FIGS. 1 and 2. First, it is determined which area of the image data of the three memory modules 1, 2, and 3 is to be displayed. That is, the memory address representing the upper left point (S2, S3 in FIG. 2) of the rectangular area to be displayed is stored in the data area start address registers 12 and 13, and the lower right point (E2, E in FIG.
3) are stored in the data area final address registers 16 and 17, respectively. Here, since the display area of memory module 1 is the entire screen area, S1 and E1 in FIG.
Setting is not necessary. Second, it is determined where on the display screen the rectangular area defined in the first setting is to be displayed. That is, the address display area start address registers 14 and 1 of the display screen indicating the upper left point of the display area on the display screen (S2', S3' in FIG. 2)
5, the address of the display screen indicating the lower right point (E2', E3' in FIG. 2) is stored in the final display address registers 18 and 19, respectively. Here, since the data of memory module 1 is to be displayed on the entire screen, the settings of S1' and E1' in FIG. 2 are unnecessary.

As described above, the data area to be displayed and the area on the screen to be displayed are determined independently. Furthermore, the contents of registers 12 to 19 can be dynamically set from the outside. For example, input settings may be made from a host processor.

Next, the operation of this embodiment will be explained. First, memory addresses 105-107 input to three memory modules 1-3 are generated as follows. In the address generation circuit 6, the data area matches all memories, so
The memory address is unconditionally incremented in synchronization with display clock 110. On the other hand, in the address generation circuits 4 and 5, the data area start address register 12 or 1, respectively.
3, and data area final address register 16
Alternatively, an address within the area is generated from the contents of 17, but this address is updated in synchronization with the display clock 110 when the display request signal 108 or 109 is active, respectively. Note that this address is updated regardless of whether the data at that address is actually displayed. Each memory module 3, 2, 1 is accessed by the memory addresses 105 to 107 thus generated, and the read display data is input to the display data selection circuit.

On the other hand, the display area detection circuits 9 and 10 detect the contents of the display area start address 14 or 15 and the display area end address 18 or 19, respectively, and the current display address (this address is the memory address input to the memory module 1). 107
It is detected whether the display address is within the display area or not. If it is detected that the display address is within the display area, a display request signal 108 or 109 is output, respectively. In response to this display request signal 108 or 109, the priority control circuit 8
A display data selection signal 101 is generated. That is, if the display request signal 108 is active, a signal for selecting the memory data 104 is used, but if the display request signal 108 is inactive and the display request signal 1 is
When signal 09 is active, a signal for selecting memory data 103 is sent, while display request signal 108 and signal 1
When both 09 and 09 are inactive, a signal for selecting memory data 102 is also output as a display data display data selection signal 101. Furthermore, in the multiplexer, this display data selection signal 1
01 selects one of the memory data 102 to 104 and outputs it as display data 100.

As is clear from the above description, "image cutting and pasting processing" as shown in FIG. 2 is realized on one display screen.

〔Effect of the invention〕

As explained above, the present invention can perform "cutting and pasting" not only of two image data but also of three or more multiple image data.

Also, the memory input to the multiplexer
More advanced image processing can be realized by adding new data, such as inverted data, or data resulting from performing logical operations or arithmetic operations between multiple pieces of memory data, between the data.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.
FIG. 2 is a screen correspondence diagram showing "image cutting and pasting processing". 1-3...Memory module, 4-6...Address generation circuit, 7...Multiplexer, 8...
Priority control circuit, 9 to 10...Display area detection circuit, 11...Display clock generation circuit, 12
~13...Data area start address register,
14-15...Display area start address register, 16-17...Data area final address register, 18-19...Display area final address register.
Register, 100...display data, 101...display data selection signal, 102-104...memory
Data, 105-107...Memory address,
108-109...display request signal, 110...display clock.

Claims (1)

[Claims] 1 main memory module for display screen;
A display device comprising a plurality of rectangular area memory modules, wherein the main memory module is provided with a display address generation circuit that generates a display address, and the plurality of rectangular area memory modules are provided with a display address generation circuit that generates a display address. a memory area register for storing address information specifying an arbitrary rectangular area of the image stored in the memory module for the rectangular area; a rectangular area address generation circuit that updates the address of the rectangular area and outputs it to the rectangular area memory module; a display area register that stores address information specifying a position on the display screen where the rectangular area is displayed; a display area detection circuit that compares the contents of a display area register with the display address and generates the display request signal indicating whether or not the display address is included in the area indicated by the contents of the display area register; and generates a display data selection signal in accordance with a plurality of display request signals generated from a plurality of display area detection circuits provided in accordance with the plurality of rectangular area memory modules and a predetermined priority order. a priority control circuit and, in response to the display data selection signal, selects or selects/processes and outputs one of the output of the main memory module and the plurality of outputs of the plurality of rectangular area memory modules; A display device comprising a selection circuit.