JPH0638428B2 - Method for manufacturing semiconductor device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a MOS field effect transistor (hereinafter referred to as MOSF).
ET), especially double diffused drain (Lighly Doped D
rain) structure semiconductor device manufacturing method.

2. Description of the Related Art With the miniaturization of MOSFETs, the electric field strength inside the device becomes higher, and the deterioration of the device characteristics due to the generated hot carriers and the decrease of the drain breakdown voltage become problems.

As a MOSFET for solving this problem, for example, IEE TRANSACTION of ELECTRON DEVICE EDAY Vol. 29, No. 4, 198
2 years, 590 pages (IEEE Transactions of Electron Devic
es ED-29, No. 4, 1982, p590), there is a MOSFET having an LDD structure.

An example in which the conventional LDD structure is applied to an n-channel MOSFET is shown in the sectional view of FIG. LDD-MOSFET
Is a gate oxide film 1 formed on the p-type silicon substrate 11.
2, a sidewall 14 made of an insulating material on both side walls of the gate electrode 13, and an n-type low concentration diffusion tank (n ⁻ layer) 15 formed by an ion implantation method using the gate electrode 13 as a mask. And an n-type high-concentration diffusion layer (n ⁺ layer) 16 similarly formed by using the sidewall as a mask, and the n ⁻ layer 15 functions to weaken the electric field strength inside the MOSFET. Thus, the generation of hot carriers is suppressed and the drain breakdown voltage is increased.

Problems to be Solved by the Invention However, in the conventional LDD-MOSFET, the resistance Rn ⁻ of the n ⁻ layer 15 enters in series between the source and drain as shown in the equivalent circuit diagram of FIG. resistance 2RN ^- higher becomes the current driving capability has a drawback that decreases.

Further, since the hot carrier generation preventing ability and the drain breakdown voltage increasing ability of the n ⁻ layer and the resistance Rn ⁻ are in inverse proportion to each other, it is difficult to obtain the optimum value of the length Ln ⁻ of the n ⁻ layer and the impurity concentration.

Means for Solving Problems The present invention has been made to overcome the above problems,
In fabricating a semiconductor device having an LDD structure on the drain region side in a semiconductor substrate, a step of forming a gate oxide film on the semiconductor substrate, forming a polysilicon film on the gate oxide film and using a photoresist as a mask Etching the polysilicon film to form a gate electrode,
Using the gate electrode as a mask, a step of ion-implanting the first impurity from an oblique direction in which the drain region does not lie behind the gate electrode, a step of forming an oxide film on the semiconductor substrate by a CVD method, and a step of forming the oxide film Anisotropically etching to form sidewalls on the gate electrode,
Implanting second impurity ions into the semiconductor substrate, wherein the first impurity ion implantation is selected to have a lower dose amount and a higher implantation energy with respect to the second impurity ion implantation. It is a method of manufacturing a semiconductor device.

Effect According to the present invention, since the first impurity ions having a relatively low concentration are implanted into the drain side below the gate electrode with high energy, the low concentration diffusion layer is formed.

Embodiment An embodiment in which the present invention is applied to an n-channel MOSFET is shown in FIG.

The MOSFET manufactured according to the present invention is formed on the p-type silicon substrate 1 and the gate oxide film 2 and the oxide film formed on the same substrate, as shown in the cross-sectional view of the main part in FIG. Gate electrode 3 made of phosphorus-doped polysilicon and CVD formed on both side walls of the gate electrode 3.
The sidewall 4 made of an oxide film, the drain side low concentration n-type (n ⁻ ) diffusion layer 5-a formed under the sidewall, and the drain side n ⁻ diffusion layer 5-a are formed in contact with each other. High-concentration n-type (n ⁺ ) diffusion layer 6- on the drain side
a and a source side n ⁺ diffusion layer 6-b.

Further, the sidewalls 4 are equal on the source side and the drain side, and the n ⁻ diffusion layer 5-a is on the drain side (Ln ⁻ D).
The n ^- diffusion layer 5-a on the drain side can significantly suppress the generation of hot carriers, and a low-concentration impurity diffusion layer is provided on the source side to increase the channel resistance of the MOSFET. It was dealt with by not having.

Next, an embodiment of the method of manufacturing the LDD-MOSFET of the present invention will be described with reference to the sectional views in order of steps of FIGS.

900 on the p-type (100) substrate 1 as shown in FIG.
A gate oxide film 2 having a thickness of about 300Å is formed by thermal oxidation at ℃.

Next, a well-known low pressure CVD method is used to form a polysilicon film having a thickness of about 6000 Å, and the first impurity, phosphorus, is doped by about 10 ²⁰ cm ^-2 by thermal diffusion. Isotropic etching is performed to form a gate electrode 3 whose side surfaces are substantially vertical as shown in FIG. 2a.

Next, by using the gate electrode 3 as a mask, the first impurity phosphorus is tilted by about 10 degrees with respect to the vertical line of the silicon substrate 1 under the conditions of an acceleration energy of 60 Kev and a dose amount of 5 × 10 ¹² cm ^-2. Inject. The ion implantation direction of phosphorus is selected such that the entire region on the drain side is not blocked by the gate electrode 3 as shown in FIG. 2B, in other words, the gate electrode 3 is behind the drain region. That is, ion implantation is performed from the diagonally right direction on the drain side to the drain side and the source side when the FIG. Further, the dose amount of phosphorus ions is selected to be lower than that of the second impurity (arsenic) ions described later. Further, the acceleration energy at the time of phosphorus ion implantation is set higher than that of arsenic. The reason is that the low concentration region is formed longer on the drain side than on the source side by phosphorus ion implantation. Although phosphorus ions are implanted over the entire region on the drain side, the phosphorus ion implantation layer is formed on the source side by a distance of about 0.1 μm from the end of the gate electrode due to the shadow effect of the gate electrode 3. This separation length is approximately equal to the thickness of the gate electrode multiplied by the implantation inclination angle (ten). After phosphorus ion implantation, 900 on the silicon substrate
Heat treatment is performed at 30 ° C. for 30 minutes to activate and diffuse the implanted phosphorus, and the n ⁻ diffusion layers 5-a and 5-b asymmetrical on the drain side and the source side as shown in FIG. To form. In FIG. 2B, the state where the n ⁻ diffusion layer 5-b on the source side reaches the lower part of the gate electrode is shown.
^- diffusion layer 5-b and the gate electrode 3 may not overlap.

Next, as shown in FIG. 2c, an oxide film 4'having a thickness of about 3000Å is formed by plasma CVD, and then anisotropic etching is performed by reactive ion etching until the surface of the silicon substrate 1 is exposed. Then, the side wall 4 as shown in FIG. 2D is formed. The width of the side wall formed at this time is affected by the shape of the gate electrode, the step coverage of the plasma oxide film, and the anisotropic degree of etching. In the case of this embodiment, the width of the side wall was 1800Å.

Next, as shown in FIG. 2D, the acceleration energy 40 of arsenic is accelerated by ion implantation using the sidewall 4 as a mask.
Silicon substrate 1 under the conditions of Kev and dose of 5 × 10 ¹⁵ cm ^-2
Inject. At this time, the arsenic ion implantation method is the reverse of the phosphorus ion implantation method. That is, as shown in FIG. 2B, the entire region on the source side is not blocked by the gate electrode 3, that is, the direction in which the gate electrode 3 is behind the source region is selected, and the inclination of ion implantation is the semiconductor substrate. Is about 10 degrees with respect to the vertical line. Due to the shadow effect of the side wall 4, the arsenic ion-implanted layer on the drain side is formed at a distance of about 0.1 μm from the end of the side wall. This separation length is approximately equal to the sidewall height multiplied by the injection tilt angle (tan). After the arsenic ion implantation, the silicon substrate 1 is heat-treated at 1000 ° C. for 20 minutes to activate and diffuse the implanted arsenic atoms to form the n ⁺ diffusion layers 6-a and 6-b. As shown in FIG. 1, the n ⁻ diffusion layer 5-a is formed only on the drain side, and a region DD-MOSFET is completed.

In the present invention, the n ^- diffusion layer is not formed on the source side. For this purpose, the width of the sidewall, the height of the sidewall, the ion implantation angle of phosphorus and arsenic, the thickness of the gate electrode, the heat treatment conditions, etc. It can be realized by setting to an appropriate value. Further, by combining these conditions, ion implantation may be performed by tilting either phosphorus or arsenic.

EFFECTS OF THE INVENTION According to the present invention, since the n ⁻ diffusion layer is formed only on the drain side where the electric field is strong, it is possible to simultaneously suppress the hot carrier effect and the channel resistance increase.

[Brief description of drawings]

FIG. 1 is a sectional view of a main part of a semiconductor device manufactured according to an embodiment of the present invention, FIGS. 2A to 2D are process drawings showing an embodiment of the present invention, and FIG. 3A is a conventional LDD-MOSFET. FIG. 3B is a cross-sectional view showing an equivalent circuit thereof. 1 ... p-type silicon substrate, 2 ... gate oxide film, 3 ...
Gate electrode, 4 ... Sidewall, 5-a, 5-b ...
... N ^- diffusion layers on drain side and source side, 6-a, 6-b
... n ⁺ diffusion layers on the drain side and the source side.

Claims (2)

[Claims] 1. A step of forming a gate oxide film on the semiconductor substrate in forming a semiconductor device having an LDD structure on the drain region side in the semiconductor substrate, a polysilicon film being formed on the gate oxide film, and a photoresist. A step of etching the polysilicon film to form a gate electrode by using the mask as a mask, and a step of ion-implanting the first impurity from a diagonal direction in which the drain region does not lie behind the gate electrode using the gate electrode as a mask, A step of forming an oxide film on the semiconductor substrate by a CVD method, a step of anisotropically etching the oxide film to form a sidewall on the gate electrode, and a step of implanting second impurity ions into the semiconductor substrate. And the first impurity ion implantation has a lower dose amount than the second impurity ion implantation, and
A method of manufacturing a semiconductor device, wherein the implantation energy is selected to be high. 2. The second impurity ions are obliquely implanted in a direction opposite to the first impurity ion implantation in the direction in which the source region does not lie behind the gate electrode. A method for manufacturing a semiconductor device as described above.