JPH0444359A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To decrease the propagation delay of a signal and control clock skew by providing the terminal of a function block connected to the wiring at the uppermost layer of plural wiring layers. CONSTITUTION:A function block comprises the lowermost A layer wiring 6, the uppermost layer A wiring 8, the contact part 10, consisting of a through hole 10b between the electrode 3 on a gate electrode 3 and the lowermost A wiring 6, a through hole 10b between the wiring 6 and A wiring 7, and a through hole 10c between the wiring 7 and wiring 8, and the input terminal 12 connected to the wiring 8, and the output terminal 13 connected to the wiring 6. Accordingly, the crowding of wiring in the vicinity of the terminal can be prevented, and it is suitable for the automatic wiring by a CAD tool. As regards the wiring capacity, the object, where CD1 between the wiring 6 and a diffusion layer 2, C12 between the wiring 6 and middle layer wiring 7, and C23 between A wiring 7 and the uppermost A wiring 8 are in series, becomes the capacitance C3 of the uppermost layer A wiring 8, and becomes the smallest value.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a master slice type semiconductor integrated circuit.

[Conventional technology]

In conventional semiconductor integrated circuits, terminals of functional blocks have terminals in the lowest layer of wiring layers, that is, the first layer Affl wiring layer. By providing the terminals of the functional blocks in the lowest wiring layer, wiring can be routed freely using the lowest wiring layer and the upper wiring layer. However, no consideration is given to wiring resistance, contact resistance, through-hole resistance, wiring capacitance, etc.

However, as logic circuits become larger in scale and become faster, ultra-high-speed operation clocks are required, and clock skew becomes a major problem.

Since the skew changes depending on wiring resistance, capacitance, contact resistance, through-hole resistance, etc., it is necessary to arrange the wiring system so that these values are as small as possible. This glare is limited by the semiconductor process, that is, unevenness remains in each manufacturing process, making planarization difficult, and flatness is better at the beginning of each manufacturing process. Therefore, the wiring in the lowest layer has the narrowest wiring width, and the wiring in the upper layer has the smallest thickness. The wiring capacitance per unit area is also large in the bottom layer and small in the upper layer. This condition is solved by moving the terminal data of the functional block from the bottom layer to the top layer so that it can be easily supported by a CAD tool that automatically routes wiring layers.

[Invention or problem to be solved]

In the conventional semiconductor integrated circuit described above, the terminal data of the functional block is located in the lowest layer of the wiring layers. As logic circuits become larger and faster, chip sizes are becoming larger, and wiring layers are becoming more multi-layered, such as three-layer wiring, and becoming smaller. Therefore, there is a problem in that the delay time for signals to propagate through wiring connecting between functional blocks increases, resulting in a circuit that requires high-speed design with little design margin.

FIGS. 2(a) and 2(b) are block diagrams for explaining problems in conventional semiconductor integrated circuits.

As shown in FIG. 2(a), the cause of clock skew is clock drive Φ1. The clock signals branched by Φ2 are the difference in the loads connected to each one and the difference in the RC time constant of the wiring. The maximum clock skew is the difference in clock signal delay from the gate closest to Φl's clock driver to the gate furthest from Φ2's clock driver.

As shown in Figure 2(b), this delay difference is calculated by the total wiring resistance R
It is expressed as approximately 0.7 times the time constant due to T and total capacitance C.

Here, we will discuss wiring resistance and wiring capacitance in multilayer wiring. The wiring in the lowest layer of the multilayer wiring is the next step after the diffusion process, and the surface has been flattened due to the process. Here, the wiring is routed by drilling a contact hole for connecting the diffusion and the wiring, or by covering the contact hole with the wiring, but the wiring width is narrowed considerably due to the process.

For example, it is possible to have a thickness of about 1.0 μm. However, although the thickness of the wiring is generally about 1.0 μm for single-layer wiring products, it is necessary to keep the thickness to about 0.6 μm. This is because planarization becomes more difficult as the layer increases to the second and third layers. There is also an example of use in which the thickness of the second layer wiring is 0.8 μm and the thickness of the third layer wiring is 1.0 μm. Therefore, the wiring on the top layer has the lowest resistance, and the wiring on the bottom layer has the highest resistance.

Next, regarding the wiring capacitance, a capacitance C is generated between the wiring layers by sandwiching the glabella insulating film between the wiring layers. Between the lowest layer Aρ wiring and the diffusion layer, the CDI between the lowest layer Affl wiring and the middle layer Aρ wiring, and the middle layer A! 2 wiring and top layer A! A capacitance of C23 is generated between the two wirings. Therefore, the capacitance C3 of the top layer Af wiring is 1/C3" 1/
Co 1+ 1 /''C1□+1/C23, which is the smallest value, and the capacitance C1 of the lowest layer Aρ wiring has the largest value.

Now, the clock wiring length is 20mm, the resistance of the bottom layer A (wiring is 40Ω/mm, the resistance of the middle layer A!2 wiring is 30Ω/')
mm, 7%The resistance of the upper layer Aρ wiring is 20Ω/mm-A The capacitance of the lower layer A7 wiring is 0, 21 pF, /ll1m, the capacitance of the middle layer Af2 wiring is 0.13 pF/question, the capacitance of the top layer A℃ wiring is 0.09pF/mm, the capacitance of the gate electrode is 0
．． Assuming that 1 pF/piece and 100 pieces of the next stage are evenly arranged, RTIX 2 is used when wiring the lowest layer Aρ.
0mm=800Ω, CTl=0.21p F/nu
n x 20 mm + 0, 1 pF / piece x 1
00 and 14.2 pF, so the maximum clock skew is about 8 ns. Therefore, care must be taken when allocating the circuits in large-scale LSI designs.

Here, when the top layer Ag wiring is provided, RT.

20Ω/mm >, 20mm=400Ω, (:tq-
0,09-ρF/tnrn\20tBra+0.1
Since pF/piece\100 pieces=118pF, the clock skew can be suppressed to a maximum of 3.3ns, and the lowest layer A
Clock skew can be reduced to less than half compared to β wiring.

In this way, it is necessary to minimize the delay caused by wiring, and for this reason, it is necessary to provide wiring with low resistance and wiring with low capacitance. In reality, it is better to provide wiring on the top layer, but if the terminal data of a functional block is on the bottom layer of the wiring layer, generally the wiring CAD tool will preferentially route the wiring on the bottom layer with the terminal data. As a result, if the wiring cannot be routed completely, an attempt is made to implement the wiring using the layer above it. Therefore, it is preferable that the terminal data of the functional block has the wiring data of the top layer from the beginning so that the clock system wiring is surrounded by the wiring of the top layer.

[Means to solve the problem]

The semiconductor integrated circuit of the present invention has a terminal of a functional block connected to the uppermost wiring of a wiring layer provided in a plurality of layers.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) and 1(b) are a plan view and an enlarged partial sectional view showing an embodiment of the present invention.

As shown in FIGS. 1(a) and (b), the example is CMO3
An example of an inverter circuit having the following configuration is shown, with P+ type diffusion layer 1 and N
+ type scattering layer 2 gate electrode 3 made of polycrystalline silicon layer
An inverter circuit is constructed using a CMOS transistor configured with a VDD wiring 4 and a GND wiring 5. Bottom layer AA wiring 6, top layer Aρ wiring 8, gate electrode 3
The gate voltage provided above is 'Igi! 3 and the bottom layer AJ wiring 6, the bottom layer Aρ wiring 6 and the middle layer A
Through hole 10b between ρ wiring 7, middle layer Affl wiring 7 and top layer A1! A functional block is constituted by a combination contact portion 10 which also serves as a through hole 10C open to the 8th layer, an input terminal 12 connected to the top layer Affl wiring 8, and an output terminal 13 connected to the bottom layer Affl wiring 6. There is.

The dual contact portion 10 has been realized through advances in semiconductor processes such as contact embedding technology and planarization technology.If the dual contact portion 10 cannot be used, it is necessary to prevent the contacts and through holes from overlapping each other. Although it is necessary to gradually raise the wiring to the upper layers, many wiring layers are crowded near the terminals, which increases the restrictions on wiring, which is disadvantageous for automatic wiring using a CAD tool. Furthermore, depending on the degree of crowding, unwired lines may occur.

As shown in FIG. 1(b), the double contact part 1
In the case where the cross section of 0 is composed of through holes 10a, 10b, and 10C vertically stacked on the gate electrode 3, it is possible to prevent wiring from crowding near the terminals and is suitable for automatic wiring using a CAD tool.

Here, we will discuss wiring resistance and wiring capacitance in multilayer wiring. The wiring in the lowest layer of the multilayer wiring is the next step after the diffusion process, and the surface has been flattened by the process. Here, a contact hole is made to connect the diffusion and the wiring, and the wiring is bent by covering the contact hole, but the wiring width needs to be narrowed by a considerable amount due to the process, for example, about 1.0 μm. It is possible up to However, the thickness of the wiring is generally about 1.0 μm for single-layer wiring products, but it is necessary to keep the thickness to about 0.6 μm. This is because planarization becomes more difficult toward the upper layers such as the second and third layers. The thickness of the second layer wiring is 0.8μm, and the thickness of the third layer wiring is 1.0μm.
There is also an example of the use of m. Therefore, the wiring on the top layer has the lowest resistance, and the wiring on the bottom layer has the highest resistance.

Next, regarding the wiring capacitance, an electrostatic capacitance C is generated between the wiring layers by sandwiching the glabellar insulating film between the wiring layers. Bottom layer A (
CD1. between the wiring and the diffusion layer. Wiring and middle layer A on the bottom layer A
C1□ between J wiring, middle layer Affl wiring and top layer A!
02 between the two wirings. produces a capacitance of Therefore, the capacitance C3 of the top layer A (wiring is 1/C3-1/Cot
+1/C12+1/C23, which is the smallest, and the capacitance C1 of the lowest layer A (the wiring has the largest value).

〔Effect of the invention〕

As explained above, the present invention relates to a master slice type semiconductor integrated circuit, and by providing the terminal data of functional blocks on the uppermost layer of the wiring layer, the wiring between the functional blocks can be connected to the uppermost layer of the wiring layer or the uppermost layer of the wiring layer. It is possible to connect using the lower layer and the next upper layer, which enables low resistance and low capacitance wiring, reduces signal propagation delay due to wiring, and also eliminates clock skew, which is a problem with clock lines. It has the effect of being held down small.

[Brief explanation of drawings]

FIGS. 1(a) and (b) are a plan view and an enlarged partial cross-sectional view showing one embodiment of the present invention, and FIGS. 2(a) and (b) are diagrams for explaining the problems of a conventional semiconductor integrated circuit. It is a block diagram. 1... P+ type diffusion layer, 2... N1 type diffusion layer, 3...
・Gate electrode, 4... VDD wiring, 5... GND wiring, 6... Bottom layer Affl wiring, 7... Middle layer Affl
l wiring, 8...Top layer Aρ wiring, 10...Double contact portion, 10a, 10b, 10cm through hole, 12...Input terminal, 13...Output terminal, 21
... Semiconductor substrate, 22 ... Field oxide film, 23
, 24.25... Interlayer insulating film, 26... Protective film.

Claims (1)

[Claims] 1. A semiconductor integrated circuit of master slice type, characterized in that it has a terminal of a functional block connected to the uppermost wiring of wiring layers provided in a plurality of layers.