JPH0444420A - Logic circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to logic circuits, for example, SPL (SPL) installed in high-speed logic integrated circuit devices such as high-speed computers.
The present invention relates to a technique that is particularly effective for use in upper Pu5h-pull Logic) circuits.

[Conventional technology]

An NTL (Non Threshold Logic
c) There is a circuit. There is also a so-called SPL circuit in which the output section of the NTL circuit is replaced with an active pull-down circuit.

The SPL circuit receives an input signal 3 as illustrated in FIG.
1; and resistors R5 and R1 provided between the ground potential of the circuit and the collector of the input transistor Tl and between the emitter of the input transistor Tl and the power supply voltage of the circuit, respectively. Equipped with The inverted output signal of this phase division circuit, that is, the collector potential of the input transistor TI, is supplied to the base of the output transistor T3, and the non-inverted output signal of the phase division circuit, that is, the emitter potential of the input transistor TI, is supplied to the base of the output transistor T3. It is supplied to the base of the output transistor T4 via a differentiating circuit. A predetermined bias voltage is applied to the base of the output transistor T4 by a bias circuit whose basic configuration is the transistor T2, so that the output transistor T4 becomes in a state immediately before being turned on. This causes output transistor T4 to act as an active load for output transistor T3,
It also constitutes an active pull-down circuit. the result,
The sensitivity of the SPL circuit is increased and its operation becomes faster.

Regarding SPL circuits, for example, Japanese Patent Application Laid-Open No. 1-26102
It is described in Publication No. 4, etc.

[Problem to be solved by the invention]

Prior to this invention, the inventors of the present application had developed the S shown in FIG. 7 above.
A 5P circuit as shown in Figure 5 with some improvements made to the PL circuit.
Developed the LWA road. That is, in FIG. 5, SP
The L circuit includes a P-channel MO5FETQI for speeding up the rise of the inverted output signal of the phase division circuit, that is, the collector potential of the input transistor T1, and an output signal S.
The SPL circuit includes a diode I)1 for clamping O and suppressing its undershoot.The SPL circuit also includes a resistor R2 and diodes D2 and D3, and a bias voltage generator that applies a predetermined bias voltage VB to the bias transistor T2. circuit and a capacitor C2 for increasing the impulse response of the circuit by feeding back the output signal SO.As a result, the SPL circuit operates even faster and more stably.

However, the inventors of the present application attempted to reduce the power consumption of the spL circuit shown in FIG. 5, and encountered the following problems. That is, in order to reduce the power consumption of the SPL circuit, it is necessary to increase the resistance value of the resistor R1 constituting the phase division circuit and to decrease its operating current. However, when the input signal Sl is changed to low level and the input transistor TI is turned off, the resistor R1
This configures a discharge path for a capacitor Ct that constitutes a differential circuit. Therefore, when the resistance value of the resistor R1 is increased, the discharge time of the capacitor C1 becomes longer.Especially, as illustrated in FIG. The effectiveness of the circuit is impaired and the fall of the output signal SO becomes slow. As a result, the impulse response and step response of the 5PLlil path deteriorate, and the reduction in power consumption of the SPL circuit is correspondingly restricted.

An object of the present invention is to provide an SPL circuit that achieves low power consumption while improving impulse response and step response.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A summary of typical inventions disclosed in this application is as follows.

That is, the resistance value of the emitter resistor of the input transistor that constitutes the phase division circuit of the SPL circuit is increased, and an N-channel discharge MO5FET that receives the output signal of the circuit at its gate is connected in parallel with this emitter resistor.
will be established.

[For production]

According to the above-mentioned means, the operating current of the phase division circuit is reduced to 11
At the same time, the discharge time of the capacitor constituting the differential circuit can be reduced. As a result, it is possible to improve the impulse response and step response of the SPL circuit while reducing its power consumption.

(Embodiment) Fig. 1 shows a circuit diagram of an embodiment of an SPL circuit to which the present invention is applied, and Fig. 2 shows an example of its signal waveform diagram. Based on this, an overview of the configuration and operation of the 5PLl path of this embodiment as well as its characteristics will be explained.

Note that the SPL circuit of this embodiment is installed in a high-speed logic integrated circuit device such as a high-speed computer together with a large number of similar SPL circuits, although this is not particularly limited. Each of the circuit elements shown in FIG. 1 is formed on a single semiconductor substrate such as single-crystal silicon along with other circuit elements constituting a high-speed logic integrated circuit device, although not limited to IIJ. In the circuit diagrams below, the MOSFET (metal oxide semiconductor field effect transistor, herein referred to as MOSFET) whose channel (back gate) is marked with an arrow
(hereinafter referred to as a general term for insulated gate field effect transistors) are P-channel type transistors, which are shown to distinguish them from N-channel MOSFETs (not shown with arrows) (in this specification, bipolar transistors are simply referred to as transistors). ) are all NPN type transistors, although they are not particularly limited.

In FIG. 3, the SPL circuit of this embodiment includes, but is not limited to, an input transistor TI that receives a predetermined input signal S1 at its base.
Although the collector of l is not particularly limited, the collector of P channel M
It is coupled to the ground potential (first power supply voltage) of the circuit via O5FETQI, and its emitter is connected to the two constant lid resistor R1 (
It is coupled to the power supply voltage (second power supply voltage) of the circuit via the first resistor means (first resistor means). These input transistors TI and MOSFET QI and resistor R1 are 5PLi! It constitutes a phase dividing circuit for the circuit, that is, an input inverting section. here,
The power supply voltage of the circuit is not particularly limited, but for example -2,
It is assumed to be a negative power supply voltage such as OV. In addition, input signal 5
1 is a relatively small amplitude digital signal with a high level of 10.8V and a low level of -1.4V, although it is not particularly specified. In this embodiment, the emitter resistor R1 is designed to have a relatively large resistance value, thereby reducing the operating current of the phase division circuit and reducing the power consumption of the SPL circuit.

Although not limited to IJ, the input signal S1 is supplied to the gate of the MO5FETQI constituting the phase division circuit. In addition, this MO5FET QI is provided with a diode Di having a predetermined forward voltage in parallel, although this is not particularly limited. As a result, MO5FETQI becomes
When the input transistor TI is turned off with the human input signal 5ll)<low level, it is selectively turned on, rapidly charging the parasitic capacitance coupled to the collector node of the λ transistor TI, and changing the output of the circuit. To speed up the rise change of the signal SO. Furthermore, when the input signal SI is at a high level, the diode DI is connected to the output signal SO of the circuit.
When set to a low level, it acts as a clamp circuit and clamps the low level of the output signal 'SO to a level of about -2XV,H (here, VIE is the forward voltage of the diode D1 etc. and the output transistor T3). (the same applies hereafter).

The SPL circuit of this example further includes a pair of output transistors T3 (first output transistor) and T4 (second output transistor) provided in a totem pole configuration between the ground potential and the power supply voltage of the circuit. this house,
The base of the output transistor T3 is coupled to the inverting output node of the phase dividing circuit, that is, the collector of the input transistor Tl, and the base of the output transistor T4 is coupled to the non-inverting output node of the phase dividing circuit via a capacitor C1 (capacitive means). That is, it is coupled to the emitter of the input transistor Tl. A resistor R4 (second resistor means), which together with the capacitor C1 constitutes a differential circuit, is provided between the base of the output transistor T4 and the power supply voltage of the circuit. Further, the emitters and collectors of the output transistors l T 3 and H T 4 are coupled to the output terminal so of the SPL circuit. As a result, output transistors T3 and T4 operate a so-called push-pull output circuit at Jl.
output transistor T4 and capacitor C1.
and resistor R4 acts as an active pull-down circuit for the other output transistor T3.

In particular, IIJv/! between the circuit ground potential and the base of the output transistor T4. Although not included, a biasing transistor T2 is provided. A predetermined bias voltage higher than the power supply voltage of the circuit by 2XVBE is applied to the base of the transistor T2 from a voltage generating circuit consisting of a resistor R2 and diodes D2 and D3 via a base resistor R3. Therefore, a bias voltage higher than the power supply voltage of the circuit by VHE is applied to the output transistor T4. As a result, the output transistor T4 is biased to the state immediately before it is turned on.

On the other hand, the base of the bias transistor T2 is coupled to the output terminal SO of the 5PLI circuit via a capacitor C2, although this is not particularly limited. This capacitor C2 constitutes a feedback circuit that transmits the level change of the output signal SO to the base of the output transistor T4, thereby speeding up the falling change of the output signal SO.

In this embodiment, the SPL circuit includes, but is not particularly limited to, an N-channel discharge MO5FET (switch means) Qll provided in parallel with the emitter resistor R1 of the input transistor TI constituting the phase division circuit.
This MO5FET QII is designed to have a relatively large conductance, and its gate is coupled to, but not limited to, the output terminal SO of the circuit. This causes MOSFET QI 1 to output the circuit's output signal S
When O is set to a high level, in other words, when the input signal Sl is set to a low level and the input transistor Tl is turned off, it is selectively turned on, short-circuiting the emitter resistor R1, and forming a differentiating circuit. Capacitor C
Speed up the I discharge operation. As a result, in the 5PLI circuit of this embodiment, although the resistance value of the emitter resistor R1 is increased in order to reduce power consumption, the impulse response and step response of the SPL circuit are improved. .

When the input signal Sl is set to high level, the input transistor TI is turned on in the phase division circuit, and the MOS
FETQI is turned off. Therefore, the inverted output signal of the phase division circuit, that is, the collector potential of the input transistor Tl, becomes a predetermined low level, and the non-inverted output signal, that is, the emitter potential of the input transistor TI, becomes a predetermined high level.

The low level of the inverted output signal of the phase division circuit is transmitted as is to the base of the output transistor T3, and the rising edge of the non-inverted output signal is transmitted to the capacitor CI and the resistor R4.
The signal is transmitted to the base of the output transistor T4 via a differentiating circuit consisting of the following. Therefore, the output transistor T3 is turned off, and the output transistor T4 is temporarily turned on. As a result, the output signal qso of the SPL circuit is
It rapidly tries to become a low level like the power supply voltage of a circuit. However, the ground potential of the circuit and the input transistor T1
As mentioned above, there is a diode DI between the collector of
A clamp circuit consisting of the following is provided. For this reason, SPL
The low level of the output signal SO of the circuit is tt approximately 2XVl
is clamped at the level of lE, thereby causing the output signal S
O's undercut is suppressed.

Note that at this time, the discharge MOSFET Qll is turned off due to the output signal SO being set to a low level, and does not have any effect.

On the other hand, when the input signal Sl is set to low level, the phase component i
In the #1 circuit, the λ transistor TI is turned off, and the MOSFET QI is turned on instead. Therefore, the inverted output signal of the phase division circuit becomes a high level like the ground potential of the circuit, and the high level of the inverted output signal of the 0 phase division circuit, whose non-inverted output signal becomes a low level, similarly remains unchanged at the output transistor. The falling transition of the non-inverted output signal is transmitted to the base of output transistor T3 via the differentiating circuit. As a result, the output transistor T4 is turned off, and the output transistor T3 is turned on instead.

As a result, the output signal SO of the SPL circuit becomes -VBE
It is considered to be a high level such as. In other words, the SPL in Figure 1
The circuit functions as an inverter circuit that inverts the logic level of the input signal Si and transmits it to the output terminal SO.

By the way, when the input signal S1 is set to low level and the input transistor Tl is turned off, the discharge M
The OSFET QI1 is turned on when the output signal SO of the SPL circuit is set to a high level. At this time, the charge accumulated in the capacitor C1 that constitutes the differentiating circuit is
Through this MO5FET QII, in other words, the input signal S 2
As illustrated in the figure, even when a negative pulse with a relatively small pulse width tel is used, the effect of the differentiating circuit is not impaired, and an output signal SO having a correspondingly small pulse width two can be obtained. As a result, it is possible to reduce power consumption of the 5PLE circuit and improve its impulse response and step response.

As described above, in the SPL circuit of this embodiment, the emitter resistance R of the input transistor TI constituting the phase division circuit is
1 is assumed to have a relatively large resistance value, which reduces the operating current of the phase divider circuit. Further, in the 5PLIi path of this embodiment, an N-channel discharge MO5FET QI1 that receives the output signal SO of the circuit is provided in parallel with the emitter resistor R1. When the input signal S1 of the circuit is at a low level and the input transistor TI is turned off, this MO5FET QI1 is selectively turned on, and the charge accumulated in the capacitor CI of the differentiating circuit is passed through the emitter resistor R1. Discharges quickly without any problems. As a result, the impulse response and step response of the SPL circuit can be improved while reducing the power consumption of the SPL circuit.

As shown in the above embodiment, the present invention can be applied to an SPL installed in a high-speed logic integrated circuit device such as a high-speed computer.
By applying it to the circuit, the following effects can be obtained. That is, (by increasing the resistance value of the emitter resistor of the input transistor constituting the phase division circuit of the 11S P L circuit, it is possible to reduce the operating current of the phase division circuit.

(2) In the above (Section 11), by providing an N-channel discharge MO5FET that receives one output signal in parallel with the emitter resistor, when the input signal is set to low level and the input transistor is turned off, the differential The effect of rapidly discharging the charges accumulated in the capacitor of the circuit and shortening the discharge time can be obtained.

3) According to the above (11) and (2), it is possible to reduce the power consumption of the SPL circuit while improving its impulse response and step response.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that this invention is not limited to the above-mentioned examples, and can be modified in various ways without getting the gist of the invention. For example, in FIG. 1, the SPL circuit can have any number of inputs and any logical function by changing the number and connection form of the input transistors that make up the phase division circuit. Also, emitter resistance R1
If the resistance value of the emitter resistor RIJt can be made extremely large, it is also possible to omit this emitter resistor RIJt and use the off-resistance of MO5FETQI1. The SPL circuit is a MOSF
A collector resistor corresponding to resistor R5 may be included in parallel form with ETQI and diode DI.Furthermore, the SPL circuit may include MOSFETs Q1 and Qll in the prototype of FIG. 7, as illustrated in FIG. Alternatively, as illustrated in FIG. 4, clamping diodes D4 and D5 may be provided between the ground potential of the circuit and the output terminal SO. A capacitor C may be used, or a level holding resistor R6 may be provided between the output terminal SO and the circuit power supply voltage.
The switch means for discharging N1 is particularly suitable for discharging N1.
It is not a prerequisite that the SPL circuit be sold as a channel MO5FET, and various embodiments can be adopted for the specific circuit configuration of the SPL circuit, the polarity and absolute value of the am voltage, the conductivity type of the transistor, etc.

In the above explanation, the invention made by the present inventor was mainly explained in the case where it was applied to an SPL circuit installed in a high-speed logic integrated circuit device, which is the field of application that formed the background of the invention, but it is not limited to this. For example, the present invention can be applied to 5PLI circuits and similar logic circuits installed in gate array integrated circuits and various dedicated logic integrated circuit devices. The present invention can be widely applied to a logic circuit including a differential circuit that transmits an inverted output signal of a dividing circuit, or to a semiconductor integrated circuit device including such a logic circuit.

[Effect of the Invention 3 The effects obtained by the typical inventions disclosed in this application are briefly explained below. That is, the resistance value of the emitter resistor of the input transistor that constitutes the phase division circuit of the SPL circuit is made relatively large, and in parallel with this emitter resistor, an N-channel discharge MOS F E that receives the output signal of the circuit is installed.
By providing T, the operating current of the phase division circuit can be reduced, and the discharge time of the capacitor constituting the differentiating circuit can be reduced. As a result, it is possible to reduce power consumption of the SPL circuit and improve its impulse response and step response.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the SPL circuit to which the present invention is applied. FIG. 2 is a signal waveform diagram showing an example of the SPL circuit shown in FIG. 1. FIG. 4 is a circuit diagram showing a second embodiment of the SPL circuit to which the invention is applied; FIG. 4 is a circuit diagram showing a third embodiment of the SPL circuit to which the invention is applied; 58th! i7 is a circuit diagram of an SPL circuit developed by the inventors of the present invention prior to this invention, FIG. 6 is a signal waveform diagram showing an example of the SPL circuit of FIG. 5, and FIG. 7 is a diagram of a conventional SPL circuit. FIG. 2 is a basic circuit diagram showing an example. T''~T4...NPN type bipolar transistor, Q
l...P channel MO5FET, Qll...N channel MOSFET, DI-D5...diode,
C1-C2... Capacitor, R1-R6... Resistor. Figure 1

Claims (1)

[Claims] 1. A phase dividing circuit including an input transistor receiving an input signal at its base and a first resistance means provided between the emitter of the input transistor and a second power supply voltage; a first output transistor provided between the power supply voltage and the output terminal of the circuit and receiving the inverted output signal of the phase dividing circuit at its base; and a first output transistor provided between the output terminal of the circuit and the second power supply voltage. a second output transistor; a capacitive means provided between the emitter of the input transistor and the base of the second output transistor; and a capacitor provided between the base of the second output transistor and a second power supply voltage. It is characterized by comprising a differentiating circuit comprising a second resistance means, and a switch means provided substantially in parallel with the first resistance means and selectively turned on according to an input signal or an output signal of the circuit. A logic circuit that 2. The switch means is an N-channel MOSFET that receives the output signal of the circuit at its gate, and
2. The logic circuit according to claim 1, wherein the resistance means has a relatively large resistance value. 3. The logic circuit according to claim 1 or 2, wherein the logic circuit is an SPL circuit installed in a high-speed logic integrated circuit device such as a high-speed computer.