JPH0448822A - logic circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to logic circuits, for example, SPLs installed in high-speed logic integrated circuit devices such as high-speed computers.
(Super Push-Pull Log
ic) relates to a particularly effective technique for use in circuits.

C. Prior Art] A non-threshold (NTL, o
gic) There is a circuit. There is also a so-called SPL circuit in which the output section of the NTL circuit is replaced with an active pull-down circuit.

Regarding SPL circuits, for example, Japanese Patent Application Laid-Open No. 1-26102
It is described in Publication No. 4, etc.

[Problem to be solved by the invention]

Prior to the present invention, the inventors of the present application developed an SPL circuit such as the fourth WJ, which was made by adding several improvements to the conventional SPL circuit as described above. That is, gJ
In Figure 4, the SPL circuit is a P-channel MO3FET for speeding up the rise of the inverted output signal of the phase division circuit, that is, the collector potential of the input transistor Tl.
The SPL circuit includes a resistor R5 and diodes D3 and D4, and applies a predetermined bias voltage to the bias transistor T2. As a result, the SPL circuit includes a bias voltage generation circuit and a capacitor C2G for increasing the impulse response of the circuit by feeding back the output signal SO.
Its operation becomes faster and more stable.

However, the inventors of the present application have found that the SPL circuit shown in FIG. 4 still has the following problems. That is, in the SPL circuit shown in FIG. 4 above,
A bias voltage generation circuit centered around the transistor T2 and a pull-down output transistor T4 form a so-called current mirror circuit. Then, the impedance ZE of this current mirror circuit as seen from the power supply voltage VEE side is
As will be described later, with respect to the resistance value R5 of the resistor R5 constituting the bias voltage generation circuit, ZE'IR5/3 is a value.

In the SPL circuit of FIG. 4, the resistance value of the resistor R5 needs to be, for example, about 16.8 KΩ (kilohms), and the impedance ZE has a relatively large value, for example, 5.6Ω. Therefore, when the pull-down output transistor T4 is turned on and the discharge current of the fixed capacitance coupled to the output terminal SO of the circuit flows through it, in other words, the output signal s of the circuit
When o is changed from high level to low level, the second
As shown by the dotted line in the figure, a relatively large power supply noise is introduced to the power supply voltage VER, which makes the operation of the SPL circuit unstable.

An object of the present invention is to reduce the impedance of an SPL circuit or the like as viewed from the power supply voltage side.

Another object of the present invention is to suppress power supply noise of an SPL circuit, etc., and stabilize its operation.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

(Means for solving ml!i) A brief overview of typical inventions disclosed in this application is as follows.

In other words, a bias circuit that applies a predetermined bias voltage to the pull-down output transistor of the SPL circuit is connected to a bias transistor provided between the first power supply voltage and the base of the output transistor, and substantially the j81 power supply voltage. a diode and a resistance means provided in series between the base of the biasing transistor; and two diodes provided in series substantially between the base of the biasing transistor and a second power supply voltage. Consisting of:

[For production]

According to the above means, it is possible to reduce the resistance value coupled between the first power supply voltage and the base of the bias transistor, so that from the voltage side of the current mirror circuit consisting of the bias circuit and the pull-down output transistor It is possible to reduce the visible impedance and suppress power fluctuations caused by the current drawn by the pull-down output transistor.

As a result, power supply noise of the SPL circuit can be suppressed and its operation can be stabilized.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of an SPL circuit to which the present invention is applied. Further, FIG. 2 shows an example of a signal waveform diagram of the SPL circuit of FIG. 1, and FIG. 3 shows a partial AC (alternating current) equivalent circuit diagram thereof. Based on these figures, an overview of the configuration and operation of the SPL circuit of this embodiment as well as its characteristics will be explained.

Note that the SPL circuit of this embodiment is installed in a high-speed logic integrated circuit device such as a high-speed computer together with a large number of similar SPL circuits, although this is not particularly limited. Although not particularly limited, each circuit element in FIG. 1 is formed on a single semiconductor substrate such as single crystal silicon along with other circuit elements constituting a high-speed logic integrated circuit device. In the following circuit diagrams, the illustrated MOSFET (metal oxide semiconductor field effect transistor, herein referred to as MOSFET)
S FET is a general term for insulated gate field effect transistors), although there are no particular restrictions on them, all of them are P-channel MO3FETs, and the transistors shown in the figure (
In this specification, all bipolar transistors (hereinafter simply referred to as transistors) are NPN type transistors.

In FIG. 1, the SPL circuit of this embodiment includes an input transistor Tl that receives a predetermined input signal Sl at its base, although the collector of the input transistor T1 is not limited to a P-channel MO3.
It is coupled to the ground potential (GND: first power supply voltage) of the circuit through the FET QI (load means of jJl), and its emitter connects to the power supply voltage of the circuit through the resistor R1 (load means of @2). (VEE: second power supply voltage). These input transistors Tl and MO3FET
QI and resistor R1 constitute a phase division circuit or input inversion section of the SPL circuit. Here, the power supply voltage of the circuit is not particularly limited, but is set to be a negative 1!1 power supply voltage such as -2.0V, for example. Further, the input signal Sl has a high level of 10, 8■ and a low level of -, for example.
It is a small amplitude digital signal of 1.4V.

Although not particularly limited, an input signal SI is supplied to the gate of MO3FETQI constituting the phase division circuit. As a result, when the input signal 31 is at a low level and the input transistor TI is turned off, the MO5FETQI is selectively turned on, and the input transistor T
It has the effect of rapidly charging the parasitic capacitance coupled to the collector node of the circuit, thereby speeding up the rise and change of the output signal SO of the circuit.

Although not particularly limited, between the ground potential of the circuit and the collector of the input transistor T1, MO3F ETQ
In parallel form with 1, a diode DI is provided. This diode D1 has a forward voltage corresponding to the base-emitter voltage VBH of an NPN bipolar transistor, and as described later, clamps the output signal SOO low level of the SPL circuit at a level of approximately -2XVsE. It acts as a clamp circuit.

The SPL circuit further includes a pair of output transistors T3 (output transistor of !J!1) and T4 (second
output transistor).

Among these, the base of the output transistor T3 is connected to the inverted output node of the phase division circuit, that is, the input transistor T3.
The base of the output transistor T4 is coupled to the non-inverting output node of the phase divider circuit, ie the emitter of the input transistor T1, through a capacitor C1. A resistor R4, which together with the capacitor C1 constitutes a differential circuit, is provided between the base of the output transistor T4 and the power supply voltage of the circuit. Also, the commonly coupled emitters and collectors of output transistors T3 and T4 are coupled to the output terminal SO of the SPL circuit. As a result, the output transistors T3 and T4 constitute a so-called push-pull output circuit, with the output transistor T3 functioning as a so-called pull-up peak transistor, and the output transistor T4 functioning as a so-called pull-down output transistor. Needless to say, the differentiating circuit consisting of the output transistor T4, the capacitor CI and the resistor R4 acts as a so-called active pull-down circuit.

In this embodiment, the SPL circuit further includes a biasing transistor T2 provided between the ground potential of the circuit and the base of the output transistor T4;
Diode D provided in series between the base of 2 and the base of
2 (first diode) and resistor R2 (resistance means),
A bias voltage generation circuit consisting of 211 diodes D3 (second diode) and D4 (third diode) provided in series substantially between the base of the bias transistor T2 and the power supply voltage of the circuit. Here, the diodes D2 to D4 are designed to have a predetermined forward voltage so that the base voltage of the biasing transistor T2 is higher than the power supply voltage of the circuit by approximately 2XVBE, although this is not particularly limited. Moreover, the resistance R2 is
It is designed to have a relatively small resistance value, for example, about IKΩ, and has the function of finely adjusting the base voltage of the transistor T2 and limiting the operating current of the bias voltage generation circuit.

For these reasons, a bias voltage higher than the circuit power supply voltage by 2XVBE is applied to the base of the bias transistor T2 via the base resistor R3, and a bias voltage higher than the circuit power supply voltage by VIE is applied to the base of the pull-down output transistor T4. A higher bias voltage is applied. As a result, output transistor T4 is biased to the state just before it turns on, thereby increasing the sensitivity of the SPL circuit.

The base of the bias transistor T2 is coupled to the output terminal SO of the SPL circuit via a capacitor C2, although this is not particularly limited. This capacitor C2 constitutes a feedback circuit that transmits the level change of the output signal SO to the base of the output transistor T4, thereby
The falling change of is accelerated.

When the input signal Sl is at a high level, the input transistor Tl is turned on in the phase division circuit, and the MOS
F ETQ 1 is turned off. Therefore, the inverted output signal of the phase division circuit, ie, the collector potential of the input transistor Tl, becomes a predetermined low level, and the non-inverted output signal, ie, the emitter potential of the input transistor T1, becomes a predetermined high level.

The low level of the inverted output signal of the phase division circuit is transmitted as is to the base of the output transistor T3, and the rising edge of the non-inverted output signal is transmitted to the capacitor CI and the resistor R4.
The signal is transmitted to the base of the output transistor T4 via a differentiating circuit consisting of the following. As a result, the output transistor T3 is turned off, and the output transistor T4 is temporarily turned on. As a result, the output signal So of the SPL circuit is
It rapidly tries to become a low level like the power supply voltage of a circuit. However, the ground potential of the circuit and the input transistor T1
As mentioned above, there is a diode DI between the collector of
A clamp circuit consisting of the following is provided. Therefore, first, the low level of the inverted output signal of the phase dividing circuit is approximately -VBE.
Furthermore, the output signal SOO low level is clamped at the level of -2XVB as illustrated in FIG.
It is clamped at the H level.

On the other hand, when the input signal Sl is set to a low level, in the phase division circuit, the input transistor Tl is turned off, and the MO3FET QI is turned on instead. For this reason,
The inverted output signal of the phase dividing circuit becomes a high level like the ground potential of the circuit, and its non-inverted output signal becomes a low level.Similarly, the high level of the inverted output signal of the 0 phase dividing circuit goes directly to the base of the output transistor T3. The falling change of the non-inverted output signal is transmitted to the base of the output transistor T4 via the differentiating circuit.

As a result, the output transistor T4 is turned off, and
Instead, the output transistor T3 is turned on. As a result, the output signal SO of the SPL circuit is set to a high level such as -VBH, as illustrated in FIG.

By the way, in the SPL circuit of this embodiment, the bias circuit centered around the bias transistor T2 and the pull-down output transistor T4 constitute a so-called current mirror circuit, and the AC (alternating current) circuit as shown in FIG.
Represented by an equivalent circuit diagram. That is, the diodes D2 to D4 in FIG. 1 are represented by constant voltages allEd2 to Ed4 corresponding to their respective forward voltages and resistances rd2 to rd4 corresponding to their respective internal resistances, and the transistors T2 and T4 are constant voltage sources Et2 and R14 corresponding to the base-emitter voltage of , and resistors re2 and re corresponding to the respective base-emitter resistances.
4 and constant current sources S2 and S4.

Hereinafter, let us find the impedance ZE of the current mirror circuit as seen from the tl voltage VER side according to the AC equivalent circuit diagram in FIG.

In Fig. 3, the fluctuation value of the power supply voltage VEE due to the current drawing of the pull-down output transistor T4 is expressed as Δ
If Ve, the base 1 of the bias transistor T2
The pressure fluctuation value ΔVX is as follows, and the base 1 pressure fluctuation value ΔV7 of the output transistor T4 is as follows.

On the other hand, if the fluctuation value of the current flowing through the bias voltage ordering circuit is Δil, and the fluctuation values of the collector currents of transistors T2 and T4 are Δ12 and Δi3, respectively, then the above equation (4) becomes re2+R4 e4 rs4 ( reZ+R4), and the impedance ZE of the current mirror circuit as seen from the power supply voltage VEE side is rd2-rd3 rd4 re2 truere4, and R2>r (R2+3r) (R4+r) (R4+r)+2 (R4+r) (R2+3r) '-R2/3.

In this embodiment, the value of the bias voltage generated by the bias voltage generation circuit is approximately set by the ratio of the forward voltages of the diodes D2 to D4, as described above.
The resistor R2 is designed to have a relatively small resistance value, for example, about IKΩ. Therefore, the impedance ZE of the current mirror circuit viewed from the power supply voltage VEE side is approximately 330Ω, which is compared to the conventional SP shown in FIG.
It is sufficiently small compared to the L circuit. As a result, the current is drawn by the pull-down output transistor T4. Fluctuations in the IM voltage VEH are significantly suppressed, as illustrated by the solid line in FIG. 2, thereby stabilizing the operation of the SPL circuit.

As described above, in the SPL circuit of this embodiment, the bias circuit that applies a predetermined bias voltage to the pull-down output transistor T4 is connected to the bias transistor T2 provided between the ground potential of the circuit and the base of the output transistor T4. , a diode D2 and a resistor R2 arranged in series substantially between the ground potential of the circuit and the base of the transistor T2; and a diode D2 and a resistor R2 arranged in series substantially between the base of the transistor T2 and the power supply voltage of the circuit. It is constituted by two diodes D3 and D4 provided.

The value of the bias voltage applied to the bias transistor T2, that is, the output transistor T4, is approximately set by the ratio of the forward voltages of the diodes D2 to D4, and the resistor R2 compensates for this and also operates the bias voltage generating circuit. They are stacked to have a relatively small resistance value that can limit the current. Therefore, transistor T2
The impedance of the current mirror circuit consisting of the bias circuit centered around , and the output transistor T4, as viewed from the power supply voltage side, is made sufficiently small, thereby suppressing power fluctuations caused by the current drawn by the output transistor T4. As a result, the power supply noise of the SPL circuit is suppressed,
The operation will be stabilized.

As shown in the above embodiment, the present invention can be applied to an SPL installed in a high-speed logic integrated circuit device such as a high-speed combinator.
By applying it to the circuit, the following effects can be obtained. That is, (1) a bias circuit that applies a predetermined bias voltage to the pull-down output transistor of the SPL circuit is connected to the first
a biasing transistor provided between a first power supply voltage and the base of the output transistor, and a diode and resistance means provided in series substantially between the first power supply voltage and the base of the biasing transistor; By comprising two diodes arranged in series substantially between the base of the bias transistor and the second power supply voltage, there is a voltage between the power supply voltage @l and the base of the bias transistor. The effect is that the resistance value to be coupled can be reduced.

(2) The above +11 term provides the effect of reducing the impedance of the current mirror circuit consisting of the bias circuit and the pull-down output transistor as viewed from the power supply voltage side.

(3) According to the above (11) and (2), it is possible to suppress fluctuations in the t source due to current drawing of the pull-down output transistor.

(Section 1, 1 to 31 above) have the effect of suppressing the power supply noise of the SPL circuit and stabilizing its operation.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above Examples (although it is possible to make various changes without departing from the gist of the invention). For example, in Fig. 1, the SPL circuit can have any number of inputs and any logical function by changing the number and connection form of the input transistors that make up the phase division circuit. The load means provided on the collector side of Tl may be a resistor, and the clamp circuit consisting of a diode Dl may include two diodes provided in series between the ground potential of the circuit and the output terminal SO of the circuit. It can also be replaced.The SPL circuit is not required to include the base resistor R3 and the feedback capacitor C2.Furthermore, the specific circuit configuration of the SPL circuit, the polarity and absolute value of the power supply voltage, and the conductivity of the transistor and MOSFET The mold etc. can take various embodiments.

In the above explanation, the invention made by the present inventor was mainly explained in the case where it was applied to an SPL circuit installed in a high-speed logic integrated circuit device, which is the field of application that formed the background of the invention, but it is not limited to this. For example, the present invention can be applied to SPL circuits and similar logic circuits installed in gate array integrated circuits and various dedicated logic integrated circuit devices. The present invention can be widely used in logic circuits including bias circuits that provide a bias circuit and semiconductor integrated circuit devices equipped with such logic circuits.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, a bias circuit that applies a predetermined bias voltage to the pull-down output transistor of the SPL circuit is connected to a bias transistor provided between the first power supply voltage and the base of the output transistor, and substantially to the first power supply voltage. a diode and a resistance means provided in series between the base of the biasing transistor and the base of the biasing transistor; and two diodes provided in series substantially between the base of the biasing transistor and a second power supply voltage. By configuring this, the resistance value coupled between the first power supply load and the base of the bias transistor is reduced, and the impedance of the current mirror circuit consisting of the bias circuit and the pull-down output transistor as seen from the power supply voltage side is reduced. Therefore, it is possible to suppress fluctuations in the power supply due to the current drawn by the pull-down output transistor. As a result, power supply noise of the SPL circuit can be suppressed and its operation can be stabilized.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an example of the SPL circuit to which the present invention is applied; Fig. 2 is a signal waveform diagram showing an example of the SPL circuit of Fig. 1; Fig. 3 is a circuit diagram showing an example of the SPL circuit of Fig. 1; Partial AC equivalent circuit diagram of SPL circuit FIG. 4 is a circuit diagram of an SPL circuit developed by the inventors of the present invention prior to this invention. Tl-74...NPN type bipolar transistor, Q
l...P channel MO3FET, Dl-D4...
Diode, C1-C2...Capacitor, R1-R5
...Resistance, S2, 54... Constant current source, Ed2~Ed
4. Et2. Et4... Constant voltage source, rd2 to rd4.
re2. re...internal resistance. Figure 1 EE Figure 2 EE

Claims (1)

[Claims] 1. A first circuit provided between a first power supply voltage and an output terminal of the circuit and selectively turned on according to a first internal signal.
a second output transistor provided between the output terminal of the circuit and the second power supply voltage and selectively turned on according to a second internal signal; a biasing transistor provided between the base of the second output transistor;
a first diode provided between the power supply voltage of the bias transistor and the base of the bias transistor, and second and third diodes provided substantially between the base of the bias transistor and the second power supply voltage. A logic circuit characterized by comprising: 2. The logic circuit according to claim 1, wherein the logic circuit includes resistance means provided in series with the first diode. 3. The first to third diodes are each designed to have a predetermined forward voltage in order to apply a predetermined bias voltage to the base of the bias transistor,
Claim 1 or 2, wherein the resistance means is designed to have a relatively small resistance value so as to finely adjust the bias voltage and limit the operating current. Logic circuit described in section. 4. The logic circuit has an input transistor that receives a predetermined input signal at its base, and first and second transistors provided on the collector and emitter sides of the input transistor, respectively.
a phase dividing circuit comprising a load means of;
Claims characterized in that the first internal signal is an inverted output signal of the phase division circuit, and the second internal signal is a differential signal of the non-inverted output signal of the phase division circuit. Logic circuit according to item 1, item 2, or item 3. 5. The logic circuit according to claim 1, 2, 3, or 4, wherein the logic circuit is an SPL circuit installed in a high-speed logic integrated circuit device such as a high-speed computer. logic circuit.