JPH0444429B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a master slice in which a memory cell for data storage is provided and the number of data lines for data transfer to and from the memory cell can be arbitrarily set. The present invention relates to a method for connecting type semiconductor memory devices. [Technical background of the invention and its problems] A master slice type semiconductor device is a semiconductor device in which elements without interconnections are formed in a semiconductor substrate in advance, and various different interconnections are formed in the subsequent interconnection formation process. A device configured to have a circuit function. By the way, when such a master slice type semiconductor device is a storage device including memory cells,
There are cases in which each memory cell is connected to a pair of data lines and data is read from one memory cell to this pair of data lines, and there are cases in which each memory cell is connected in parallel to multiple pairs of data lines to read data from one memory cell. There are two possible ways to read data from a cell to multiple pairs of data lines. The following master slice type semiconductor memory device compatible with such two types of data reading can be considered. Figure 1 shows one pair or two from one memory cell.
FIG. 2 is a circuit diagram showing a 1-bit memory cell of a master slice type semiconductor memory device that can read data to a pair of data lines. Note that, for convenience of explanation, this memory cell is shown with some wiring already formed. This memory cell consists of a data storage flip-flop 3 constructed by connecting two inverters 1 and 2 in antiparallel, and a selection flip-flop 3 whose one end is connected to one data storage point 4 of the flip-flop 3. 2 MOS
Transistors 5 and 6 and the flip-flop 3
Two MOS transistors 8 and 9 for selection also have one end connected to the other data storage point 7, and the two MOS transistors 5,
The word line 10 has the gate electrodes of the MOS transistors 6 and 9 connected in common, and another word line 11 has the gate electrodes of the MOS transistors 6 and 9 connected in common. In such a memory cell, the flip-flops 3 are interconnected and connected to one or two pairs of data lines through a wiring forming step which is the final stage of the manufacturing process. In other words, when connecting two pairs of data lines, as shown in Figure 2, two pairs of data lines are connected.
DL ₁ , ₁ , DL ₂ , ₂ are provided, and the other ends of the MOS transistors 5, 8, 6, 9 are connected to these data lines DL ₁ , ₁ , DL ₂ , _2, respectively. At this time, the same drive signal or different drive signals are applied to the two word lines 10 and 11, and the two pairs of data lines DL ₁ , ₁ , DL ₂ ,
Data is read for each DL ₂ . On the other hand, when the memory cell is connected to a pair of data lines, as shown in FIG. 3, only one pair of data lines DL is provided, and both data lines DL,
For example, the other ends of the MOS transistors 5 and 8 are connected to DL, respectively. At this time, a drive signal is applied to only one word line 10, and the other word line 11 is not used. Note that in Figures 2 and 3, the memory cells are RAM cells, so
It is possible to not only read data from memory cells but also write data. By the way, when a storage device is configured as shown in FIG. 2 using memory cells configured as shown in FIG. It is approximately twice as large as the case shown in the figure. Therefore, when simultaneously reading data from two pairs of data lines, inverters 1 and 2 constituting the flip-flop 3 should be designed to have large dimensions in order to sufficiently drive each data line and enable high-speed reading. There is a need. However, if the dimensions of the inverters 1 and 2 are increased and the storage device is configured with a pair of data lines as shown in FIG. 3, the read speed will be higher than in the case of FIG. 2, but the cell size will be increased. As the size increases, the number of memory cells that can be accommodated within one chip decreases. In other words, Figures 2 and 3
Comparing the figures, the cell sizes of the memory cells are the same, and in FIG. 3, the wasted area becomes large, making it impossible to achieve high integration. [Object of the Invention] The present invention has been made in consideration of the above-mentioned circumstances, and its purpose is to provide appropriate operation when connecting memory cells to one or more pairs of data lines. It is an object of the present invention to provide a connection method for a master slice type semiconductor memory device that has high speed and can achieve high integration without wasting area. [Summary of the Invention] According to the present invention, by configuring a unit memory by interconnecting data storage points of basic memory cells whose number is equal to the number of data line pairs, the A master slice type semiconductor memory device that has a constant data read speed that is not excessive, and can achieve high integration without wasting area because the basic memory cell is used as a unit memory when a pair of data lines is provided. is provided. [Embodiment of the Invention] An embodiment of the invention will be described below with reference to the drawings. FIG. 4 is a circuit diagram showing one bit of a basic memory cell of a master slice type semiconductor memory device according to the present invention. Note that in this case as well, for convenience of explanation, some wiring is shown in a state where it has already been formed. This basic memory cell is as shown in the figure.
Flip-flop 23 for data storage configured by connecting two inverters 21 and 22 in antiparallel
and a selection MOS whose one end is connected to one data storage point 24 of this flip-flop 23 .
transistor 25 and the flip-flop 23
2, and a word line 28 to which the gate electrodes of both the MOS transistors 25 and 27 are commonly connected. A large number of such basic memory cells are arranged in an element region. The dimensions of the two inverters 21 and 22 constituting the flip-flop 23 are designed to be sufficient to drive a pair of data lines. FIG. 5 shows that the inverters 21 and 22 are
In the case of the CMOS configuration and the flip-flops 23 are not interconnected, the fourth
FIG. 3 is a pattern plan view showing the element structure of the basic memory cell shown in the figure. In FIG. 5, reference numeral 31 is a P-well region formed within an N-type semiconductor region, and within this P-well region 31 are the source and drain regions of N-channel MOS transistors Q _N1 to Q _N8 , and the interconnection of these regions. The N + type region 32 and the like as interconnects connected to the N ⁺ type region 32 are formed by, for example, a diffusion method. N
In the type semiconductor region, there are source and drain regions of P channel MOS transistors Q _P1 to Q _P4 , and a P ⁺ type region 33 as wiring interconnecting these.
is also formed using the diffusion method. Further, on these regions, a polycrystalline silicon layer 34 is formed as a gate electrode, a word line, and other interconnections, which are laminated via a field insulating film or a gate insulating film.
is formed. FIG. 6 is an equivalent circuit diagram of an element having a pattern as shown in FIG. As is clear from FIG. 6, in FIG. 5, the basic memory cells in FIG.
Of the inverters and word lines corresponding to those shown in FIG. 4, one bit side has the letter A added to the end of the code, and the other bit side has the letter B added to the end. When configuring a storage device by connecting the basic memory cell shown in the equivalent circuit diagram of FIG. 6 with a pair of data lines, the following wiring formation process is performed to form the basic memory cell shown in the equivalent circuit diagram of FIG. 7. Circuit connections are made. That is, first, the N-channel is created by the first layer of metal wiring.
The sources of each of the MOS transistors Q _N1 to Q _N4 are connected to the low potential V _SS application point, and the P-channel MOS transistors are also connected by the first layer of metal wiring.
Q _P1 drain, N-channel MOS transistor
Q _N1 drain, P channel MOS transistor
The common gate electrodes of Q _P2 and N-channel MOS transistor Q _N2 are interconnected, and the P-channel MOS
Drain of transistor Q _P2 , drain of N-channel MOS transistor Q _N2 , P-channel MOS transistor Q _P1 and N-channel MOS transistor
The common gate electrodes of Q _N1 are interconnected. Furthermore, P channel is formed by the first layer of metal wiring.
Drain of MOS transistor Q _P3 , N channel
Drain of MOS transistor Q _N3 , P channel
The common gate electrodes of MOS transistor Q _P4 and N-channel MOS transistor Q _N4 are interconnected, and the drain of P-channel MOS transistor Q _P4 , the drain of N-channel MOS transistor Q _N4 , the P-channel MOS transistor Q _P3 , and the N-channel MOS transistor Q The common gate electrodes of _N3 are interconnected. Next, the one selection MOS transistor 25 is connected to the second layer of metal wiring.
The data line DL to which the open ends of the N-channel MOS transistors Q _N5 and Q _N7 are connected is connected to the other selection MOS transistor 27 N
Data lines are wired to which the open ends of channel MOS transistors Q _N6 and Q _N8 are connected. FIG. 8 is a pattern plan view of an element in which circuit connections as shown in FIG. 7 are made. In FIG. 8, 35 is the first layer metal wiring, 36 is the second layer metal wiring, and 37 is the N ⁺ type region 32,
This is a contact hole that connects between the P ⁺ region 33 and the first layer metal wiring 35 or between the first and second layer metal wirings 35 and 36. In this way, a basic memory cell is connected to a pair of data lines.
DL, to configure a storage device, one basic memory cell becomes a unit memory cell, so there is no waste in the area of each basic memory cell, and all basic memory cells are It can be a bit memory cell. Furthermore, the dimensions of the two inverters 21 and 22 constituting the flip-flop 23 in each basic memory cell are designed to be sufficient to drive one pair of data lines. Data can be read from each basic memory cell at the optimum speed determined by the data. Next, when configuring a storage device by connecting the basic memory cell shown in the equivalent circuit of FIG. 6 to two pairs of data lines, a ninth
The circuit connections are made as shown in the figure. That is, the first
First, the same circuit connection as in the case of FIG. 7 is made by the layered metal wiring, and the P-point channel MOS transistor Q _P1 , which is the one data storage point 24 of one flip-flop 23A , and the N-channel MOS transistor are connected. A P channel MOS in which the drain connection point of the transistor Q _N1 is the one data storage point 24 of the other flip-flop 23B .
It is mutually connected to the drain connection point of transistor Q _P3 and N-channel MOS transistor Q _N3 .
Furthermore, the other data storage points 26 of flip-flops 23A and 23B are interconnected. Next, the open ends of the N-channel MOS transistors Q _N5 and Q _N6 , which are the selection MOS transistors 25 and 27 in one basic memory cell, are connected by the second layer metal wiring. The pair of data lines DL ₁ , ₁ are connected to the selection MOS transistors 25 , 25 in the other basic memory cell.
27 N-channel MOS transistor Q _N7 ,
The other pair of data lines DL ₂ and ₂ to which the open ends of Q _N8 are connected are respectively wired. In addition,
FIG. 10 shows a pattern plan view of an element in which circuit connections as shown in FIG. 9 are made. Further, in FIG. 10, numeral 35 indicates a first layer metal wiring, numeral 36 a second layer metal wiring, and numeral 37 a contact hole. When configuring a storage device by connecting two basic memory cells with two pairs of data lines DL ₁ , ₁ , DL ₂ , ₂ in this way, the data storage points of the two basic memory cells are interconnected. constitute a unit memory cell. In this case, the two basic memory cells act as one memory cell, and the dimensions of the two inverters 21 and 22 constituting each flip-flop 23A and 23B are sufficient to drive one pair of data lines. Because of the design, the read speed when simultaneously reading data from this unit memory cell to the two pairs of data lines DL ₁ , ₁ , DL ₂ , ₂ is the same as the optimal one as in the case of FIG. 7 above. can do. As described above, according to this embodiment, when one pair or two pairs of data lines are provided, high integration can be achieved without wasting area when one pair is provided. In this case, the data read speed can be optimized. FIG. 11 is a circuit diagram showing the configuration of an applied example of the present invention, and shows the entire memory device provided with two pairs of data lines as shown in FIG. 9. That is, the data storage points 24 of the two basic memory cells 40, 50
24 and 26 and 26 are connected to each other, one word line 28 is one output line of one of the two X direction decoders 71 and 72. 73, and the other word line 28 is connected to one output line 74 of the other X-direction decoder 72. Furthermore, the pair of data lines DL ₁ , ₁ are connected to a pair of input/output lines I/O ₁ , 1 via selection MOS transistors 81 , 82 .
Connect to I/O ₁ and the remaining pair of data lines DL ₂ ,
DL ₂ is connected to another set of input/output lines I/O ₂ , ₂ via selection MOS transistors 83 , 84 . Furthermore, the MOS transistors 81, 8
2 gate electrodes are connected to two Y-direction decoders 91, 9.
2, is connected to one output line 93 of one Y-direction decoder 91, and the MOS transistors 83, 8
4 gate electrode of the other Y-direction decoder 92
Connect to the output line 94 of the book. In the storage device configured in this way, by providing two X-direction decoders 71, 72 and Y-direction decoders 91, 92, 1-bit data can be sent to two sets of input/output lines I/O ₁ , _1. ，
Can be read simultaneously to I/O ₂ , ₂ .
Furthermore, since data can be written simultaneously from the two pairs of data lines DL ₁ , ₁ and DL ₂ , ₂ , high-speed writing can be realized. Note that the present invention is not limited to the above-mentioned embodiments, and various modifications are possible. For example, in the embodiment described above, one or two pairs of data lines are provided, but three or more pairs may be provided. When three or more pairs are provided, the number of basic memory cells as shown in FIG. Data read speed can be obtained. [Effects of the Invention] As explained above, according to the present invention, when a memory cell is coupled to one or more pairs of data lines, it can be operated at an appropriate operating speed and at high speed without wasting area. A master slice type semiconductor integrated circuit that can be integrated can be provided.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a 1-bit memory cell of a conventional master slice type semiconductor memory device, and FIGS. 2 and 3 are circuit diagrams for connecting the memory cell of FIG. 1 to a data line, respectively. 4 is a circuit diagram showing one bit of a basic memory cell of a master slice type semiconductor memory device according to the present invention, FIG. 5 is a pattern plan view of the cell shown in FIG. 4, and FIG. 6 is an equivalent circuit of FIG. 5. 7 is a circuit diagram of a memory device constructed using the basic memory cell shown in FIG. 6, FIG. 8 is a pattern plan view of the circuit shown in FIG. 10 is a pattern plan view of the circuit of FIG. 9, and FIG. 11 is a circuit diagram showing the configuration of an applied example of the present invention. 21, 22...Inverter, 23...Flip-flop, 24, 26...Data storage point, 25,
27...MOS transistor for selection, 28...
Word line, DL,, DL ₁ , ₁ , DL ₂ , ₂ ...
...Data line, Q _N1 to _{Q N8} ... N channel MOS transistor, Q _P1 to Q _P4 ... P channel MOS transistor.

Claims (1)

[Claims] 1 A basic memory cell configured with some wiring remaining and an arbitrary pair of data lines for data transfer between this basic memory cell and the basic memory cell are provided,
A method for connecting a master slice type semiconductor memory device, characterized in that data storage points of a number of basic memory cells corresponding to the data line pairs are connected to each other to form a unit memory cell.