JPH0446567A - Phase control circuit - Google Patents

Abstract

PURPOSE:To enable stabilized operation by converting frequency detected from a synchronous power supply into pulses, converting pulses into an analog value and installing a bias circuit following up frequency to the frequency of the synchronous power supply in place of free-running oscillation frequency and controlling frequency. CONSTITUTION:The synchronous voltage signals of three phase are converted into 180 deg. pulses by a level detector 10 respectively, and oscillation frequency formed by the pulses of an oscillator 12 is counted during 180 deg. pulses, and converted into a digital value. Signals detected at every phase are added to a V/F converter 5 as bias signals through an intermediate-value selector circuit 19 and a filter circuit 22. Accordingly, the change of frequency can be detected at every cycle, the loop filter constant of a phase-difference amplifier circuit can be selected within a wide range, and excellent synchronous characteristics can be acquired even when the follow-up range of frequency is wide.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention is provided in an AC power system, and is applied to a static starter or a phase converter of an AC/DC converter having a wide frequency variable range, such as a cycloconverter. Regarding control circuits.

(Prior Art) A phase control circuit in a conventional AC/DC converter will be described with reference to FIG.

The synchronous power supply is input to the three-phase two-phase conversion circuit 1 and converted into sin θ and cos θ on the d-axis and q-axis, respectively, and the phase difference detection circuit 2 feeds back the output of the voltage conversion circuit 7.8 that creates sin θ and cos θ. Detects the phase difference as a signal. The phase difference between the synchronous voltage detected by the phase difference detection circuit 2 and the voltage generated by the PLL feedback loop 7.8 is amplified by the error amplifier 3. The voltage signal with the phase difference amplified is input to the V/F converter 5 which converts the voltage into a frequency, and the counter circuit 6 converts the oscillation frequency according to the phase difference, which is configured to change the frequency according to the phase difference. It is configured to count and create a frequency-divided pulse train synchronized with the synchronous power supply. The bias signal 4 input to the V/F converter 5 is called a free-running oscillation frequency and has a fixed bias value.

The free-running oscillation frequency is generally set to a value that is the oscillation frequency that is synchronized when the phase difference between the synchronous power supply and the PLL feedback loop is zero, that is, when the output of the loop filter 3 is zero.

Further, the phase control circuit 9 is a circuit that creates timing for outputting gate pulses from a pulse train synchronized with the power supply in a PLL loop.

In this way, the conventional configuration has been such that the free-running oscillation frequency is fixed and the phase difference between the synchronous power supply and the phase control circuit is corrected using a voltage signal whose error is amplified by a loop filter.

(Problem to be Solved by the Invention) In the conventional phase control circuit described above, when the frequency fluctuation range is large, with a fixed free-running oscillation frequency and a fixed loop filter constant, if the frequency is fixed, the loop filter has a phase difference. However, it is necessary to correct large frequency fluctuations and phase differences using a loop filter. For this reason, it is necessary to make the output of the loop filter move over a wide range, and for this reason Ga1 for each frequency
Since n is different, it is difficult to cover all aspects such as synchronization pull-in characteristics, responsiveness, followability, etc.

Therefore, an object of the present invention is to provide a phase control circuit used in the above-mentioned circuit, which can operate stably.

[Structure of the invention]

(Means for Solving the Problems) The present invention converts the frequency detected from a synchronous power supply into pulses, converts the pulses into analog values, and performs free-running oscillation instead of a free-running oscillation frequency setter provided in a PLL circuit. The present invention provides a phase control circuit characterized by having a bias circuit that performs control by following the frequency of a synchronous power source instead of the frequency.

(Function) According to the above configuration, for basic frequency fluctuations,
Since the bias circuit follows at high speed, the loop filter only needs to move to compensate for the phase difference in the frequency range to be followed, and the same conditions apply to a wide range of frequency bands, which improves synchronization followability. This improves the stability of the converter and enables stable operation of the converter.

(Example) Examples will be explained below.

FIG. 1 is a block diagram showing one embodiment of a phase control circuit according to the present invention. The same elements as those in the conventional example shown in FIG. 4 are given the same numbers and their explanations will be omitted.

As shown in the figure, in addition to the configuration of the conventional example shown in FIG. Count during 180° pulse and convert to digital value. The signal detected for each phase is added to the V/F converter 5 as a bias signal through an intermediate value selection circuit 19 and a filter circuit 22. FIG. 3 is a time chart illustrating details of the free-running oscillation frequency correction circuit of FIG. 1. The operation of the free-running oscillation frequency correction circuit of this embodiment will be explained with reference to FIGS. 2 and 3.

The waveform shown in FIG. 3 (a) is input to the level detection circuit lO, and the output is converted into 180 @ pulses of “1” and “0” shown in (b). The same figure (c) is the output of the oscillator 12. This is a signal for the monomulti circuit 11 to start counting by the counter circuit 13 at the timing shown in (d).

Since the mono multi-circuit 17 is provided with the inversion circuit 16 at its input, the timing shown in (e), that is, the timing shown in (b) 18
At the falling edge of the 0° pulse, a one-shot pulse is output and used as a latch signal for the latch circuit 14.

In other words, the counter circuit 1 counts the number of pulses oscillated by the oscillator within the period (d) to (e) (180 degrees).
3 and holds the count value until the next cycle. The output of the counter circuit is expressed in analog form as shown by the dotted line in (G).

When the rat is applied, the output of the counter circuit 13 is reset after the timer of the monomulti circuit 18 is reset and becomes zero as shown by the dotted line (G). Since the outputs of the latch circuit 14 and the D/A conversion circuit 15 are held before the counter circuit 14 is reset, the outputs are as shown by the solid line in (g). Therefore, a change in frequency is detected every cycle.

In the present invention, by detecting all three phases of the synchronous power supply in the same way and detecting the intermediate value of the three phases, the system is configured so that there is no problem even if a negative phase ground fault occurs in the event of an AC system fault. There is. The output of the intermediate value selection circuit 19 is added to the value of the bias circuit 21 in an adder 20, and is converted to a characteristic in which the frequency becomes higher as the voltage becomes higher than the characteristic of the V/F converter.

Further, the amplifier circuit 22 is a filter circuit for preventing the bias signal from changing suddenly every cycle, and the free-running oscillation frequency correction signal moves as shown in (h).

Although the present invention has been described with reference to a circuit configuration in which the free-running oscillation frequency is corrected in three phases, it goes without saying that the present invention also includes a circuit configuration in which only the negative phase is corrected.

〔Effect of the invention〕

As explained above, according to the present invention, since frequency fluctuations are detected at high speed and the free-running oscillation frequency is corrected, the loop filter constant of the phase difference amplifier circuit can be selected from a wide range.
Good synchronization characteristics can be obtained even when the frequency tracking range is wide, and stable operation of the AC/DC converter can be ensured.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the phase control circuit according to the present invention, FIG. 2 is a detailed block diagram of the embodiment of FIG. 1, and FIG. 3 is a diagram for explaining the operation of FIG. 1. The time chart in FIG. 4 is a block diagram of a conventional phase control circuit. 1... Three-phase/two-phase conversion circuit, 2... Phase difference detection circuit, 3... Loop filter, 4
...Free-running oscillation frequency, 5...V/F converter, 6
... Counter circuit, 7.8 ... Voltage conversion circuit,
9... Phase control circuit, 10... Level detection circuit,
11.17.18...Mono multi circuit. 12... Oscillation circuit, 13... Counter circuit, 14
...Latch circuit, 15...D/A conversion circuit. 16... Inverter IC119... Intermediate value selection circuit, 20.23... Addition circuit, 21... Bias setting device, 22... Filter circuit. Agent Patent Attorney Noriyuki Chika (c) Figure 1 Figure 3 Chopsticks 4 Figure 2

Claims (1)

[Claims] A phase control circuit equipped with a PLL circuit, which detects a frequency from a synchronous power supply instead of a bias value corresponding to a free-running oscillation frequency, and applies that value as a bias to the phase control circuit.