JPH0446727U - - Google Patents
Info
- Publication number
- JPH0446727U JPH0446727U JP8901890U JP8901890U JPH0446727U JP H0446727 U JPH0446727 U JP H0446727U JP 8901890 U JP8901890 U JP 8901890U JP 8901890 U JP8901890 U JP 8901890U JP H0446727 U JPH0446727 U JP H0446727U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- offset
- calculating
- digital
- integrating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図は本考案によるオフセツトキヤンセラの
１実施例のブロツク図、第２図は同実施例の動作
説明図である。
２……加算手段（算出手段）、４……乗算手段
、６……比較手段、８……アツプ／ダウンカウン
ト手段（積分手段）。
FIG. 1 is a block diagram of one embodiment of an offset canceller according to the present invention, and FIG. 2 is an explanatory diagram of the operation of the same embodiment. 2... Adding means (calculating means), 4... Multiplying means, 6... Comparing means, 8... Up/down counting means (integrating means).
Claims (1)
ル信号との代数和を算出する算出手段と、この算
出手段の出力信号が基準信号よりも大きいとき第
１の状態信号を生成し上記出力信号が上記基準信
号よりも小さいとき第２の状態信号を生成する比
較手段と、第１または第２の状態信号を積分しそ
の積分値を上記オフセツトキヤンセル信号として
上記算出手段に供給する積分手段とを、具備する
デイジタルオフセツトキヤンセラ。 (2) 請求項１記載のデイジタルオフセツトキヤ
ンセラにおいて、０よりも大きく１以下の値に選
択した係数を上記積分手段の積分値に乗算しその
乗算値を上記オフセツトキヤンセル信号として上
記算出手段に供給することを特徴とするデイジタ
ルオフセツトキヤンセラ。[Claims for Utility Model Registration] (1) Calculating means for calculating an algebraic sum of a digital input signal and an offset cancel signal, and generating a first state signal when the output signal of this calculating means is larger than a reference signal. and a comparison means for generating a second state signal when the output signal is smaller than the reference signal; and a comparison means for integrating the first or second state signal and supplying the integrated value to the calculation means as the offset cancel signal. A digital offset canceller comprising: an integrating means for calculating the offset value; (2) In the digital offset canceller according to claim 1, the calculating means multiplies the integral value of the integrating means by a coefficient selected to be greater than 0 and less than or equal to 1, and uses the multiplied value as the offset cancel signal. A digital offset canceller characterized by supplying.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8901890U JPH0446727U (en) | 1990-08-23 | 1990-08-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8901890U JPH0446727U (en) | 1990-08-23 | 1990-08-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0446727U true JPH0446727U (en) | 1992-04-21 |
Family
ID=31822710
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8901890U Pending JPH0446727U (en) | 1990-08-23 | 1990-08-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0446727U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5297662A (en) * | 1976-02-10 | 1977-08-16 | Nec Corp | Offset compensation circuit |
| JPS62290216A (en) * | 1986-06-09 | 1987-12-17 | Nec Corp | Auto-zero device |
-
1990
- 1990-08-23 JP JP8901890U patent/JPH0446727U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5297662A (en) * | 1976-02-10 | 1977-08-16 | Nec Corp | Offset compensation circuit |
| JPS62290216A (en) * | 1986-06-09 | 1987-12-17 | Nec Corp | Auto-zero device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA2041477A1 (en) | Active acoustic attenuation system with overall modeling | |
| JPH0446727U (en) | ||
| JPH0262875U (en) | ||
| JPS61104638U (en) | ||
| JPH033004U (en) | ||
| JPS62173810U (en) | ||
| JPH0344916U (en) | ||
| JPH03431U (en) | ||
| JPS5856587U (en) | Automotive power supply circuit | |
| JPH0249326U (en) | ||
| JPH01135827U (en) | ||
| JPH0313507U (en) | ||
| JPS62100775U (en) | ||
| JPS5834057U (en) | Maximum value/minimum value detection circuit | |
| JPS58128922U (en) | belt for slacks | |
| JPS63147021U (en) | ||
| JPH0332866U (en) | ||
| JPH0226842U (en) | ||
| JPH0365976U (en) | ||
| JPS6446863U (en) | ||
| JPS6316328U (en) | ||
| JPS62169571U (en) | ||
| JPH02143628U (en) | ||
| JPH0232060U (en) | ||
| JPH0485939U (en) |