JPH0446727U - - Google Patents

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Publication number
JPH0446727U
JPH0446727U JP8901890U JP8901890U JPH0446727U JP H0446727 U JPH0446727 U JP H0446727U JP 8901890 U JP8901890 U JP 8901890U JP 8901890 U JP8901890 U JP 8901890U JP H0446727 U JPH0446727 U JP H0446727U
Authority
JP
Japan
Prior art keywords
signal
offset
calculating
digital
integrating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8901890U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8901890U priority Critical patent/JPH0446727U/ja
Publication of JPH0446727U publication Critical patent/JPH0446727U/ja
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Description

【図面の簡単な説明】
第１図は本考案によるオフセツトキヤンセラの
１実施例のブロツク図、第２図は同実施例の動作
説明図である。 ２……加算手段（算出手段）、４……乗算手段
、６……比較手段、８……アツプ／ダウンカウン
ト手段（積分手段）。

Claims (1)

  1. 【実用新案登録請求の範囲】 (1) デイジタル入力信号とオフセツトキヤンセ
    ル信号との代数和を算出する算出手段と、この算
    出手段の出力信号が基準信号よりも大きいとき第
    １の状態信号を生成し上記出力信号が上記基準信
    号よりも小さいとき第２の状態信号を生成する比
    較手段と、第１または第２の状態信号を積分しそ
    の積分値を上記オフセツトキヤンセル信号として
    上記算出手段に供給する積分手段とを、具備する
    デイジタルオフセツトキヤンセラ。 (2) 請求項１記載のデイジタルオフセツトキヤ
    ンセラにおいて、０よりも大きく１以下の値に選
    択した係数を上記積分手段の積分値に乗算しその
    乗算値を上記オフセツトキヤンセル信号として上
    記算出手段に供給することを特徴とするデイジタ
    ルオフセツトキヤンセラ。
JP8901890U 1990-08-23 1990-08-23 Pending JPH0446727U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8901890U JPH0446727U (ja) 1990-08-23 1990-08-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8901890U JPH0446727U (ja) 1990-08-23 1990-08-23

Publications (1)

Publication Number Publication Date
JPH0446727U true JPH0446727U (ja) 1992-04-21

Family

ID=31822710

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8901890U Pending JPH0446727U (ja) 1990-08-23 1990-08-23

Country Status (1)

Country Link
JP (1) JPH0446727U (ja)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5297662A (en) * 1976-02-10 1977-08-16 Nec Corp Offset compensation circuit
JPS62290216A (ja) * 1986-06-09 1987-12-17 Nec Corp オ−トゼロ装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5297662A (en) * 1976-02-10 1977-08-16 Nec Corp Offset compensation circuit
JPS62290216A (ja) * 1986-06-09 1987-12-17 Nec Corp オ−トゼロ装置

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