JPH0446739U

JPH0446739U -

Info

Publication number: JPH0446739U
Application number: JP8993690U
Authority: JP
Priority date: 1990-08-28
Filing date: 1990-08-28
Publication date: 1992-04-21

Description

【図面の簡単な説明】第１図は本考案のフレーム同期保護回路の一実
施例を示す回路図、第２図は第１図の主要部の波
形の一例を示すタイムチヤート、第３図は従来の
一例を示す回路図、第４図および第５図は第３図
の主要部の波形の一例を示すタイムチヤート、第
６図はフレーム同期保護回路の接続状況の一例を
示すブロツク接続図である。１０，２０……ＲＳ形フリツプフロツプＲＳ−
Ｆ／Ｆ回路、１１〜１５，２１〜２７……Ｄ形フ
リツプフロツプＤ−Ｆ／Ｆ回路、１６，１７，２
８……論理積ＡＮＤ回路、１９……５分周回路、
２９……論理和ＯＲ回路。[Brief Description of the Drawings] Fig. 1 is a circuit diagram showing an embodiment of the frame synchronization protection circuit of the present invention, Fig. 2 is a time chart showing an example of waveforms of the main parts of Fig. 1, and Fig. 3 is a circuit diagram showing an example of the frame synchronization protection circuit of the present invention. Figures 4 and 5 are time charts showing an example of the waveforms of the main parts of Figure 3, and Figure 6 is a block connection diagram showing an example of the connection status of the frame synchronization protection circuit. be. 10,20...RS type flip-flop RS-
F/F circuit, 11-15, 21-27...D flip-flop D-F/F circuit, 16, 17, 2
8...Logic AND circuit, 19...5 frequency divider circuit,
29...Logical OR circuit.

Claims

[Claims for Utility Model Registration] 1. A local frame pulse generated from a clock pulse synchronized with the received data signal from a frame synchronization circuit that establishes frame synchronization based on the frame pulse included in the received data signal;
Coincidence of frame pulses in the received data signal/
In a frame synchronization protection circuit that receives mismatch information and sends a determination result of frame synchronization to the frame synchronization circuit based on a predetermined number of protection stages, at least one of the above 1. A frame synchronization protection circuit, further comprising a determination circuit that determines that frame synchronization is out of synchronization when detecting mismatch information of frame pulses. 2. From a frame synchronization circuit that establishes frame synchronization based on the frame pulse included in the received data signal, a local frame pulse generated from a clock pulse synchronized with the received data signal is sent to the terminal T, and the frame synchronization circuit establishes frame synchronization based on the frame pulse included in the received data signal. A predetermined number of first pulses are connected in series, in which either the mismatched pulse or the output of the terminal Q of the previous stage is input to the terminal D, and the output of the terminal Q is input to the terminal D of the next stage.
a D-type flip-flop D-F/F circuit, a first AND circuit inputting the output of the terminal Q of the first D-F/F circuit, and the first D-F/F circuit. a second AND circuit that inputs the outputs of a predetermined number of terminals Q of successive previous stages; a frequency divider circuit that divides the frequency of the local frame pulse by a predetermined number; and the output of this frequency divider circuit that inputs the outputs of the terminal R. and inputs the mismatched pulse of the frame pulse to the terminal S.
RS type flip-flop RS-F/F circuit,
Either the output of the terminal Q of this first RS-F/F circuit or the output of the terminal Q of the previous stage is inputted to the terminal D, and the output of the terminal Q is inputted to the terminal D of the next stage. 2 D-F/F circuit and the first RS
- a third AND circuit that receives the outputs of the terminals Q of the F/F circuit and the second D-F/F circuit; and a logical sum that receives the outputs of the first and third AND circuits; a second R circuit, which inputs the output of the OR circuit to the terminal S, inputs the output of the second AND circuit to the terminal R, and outputs the determination result from the terminal Q.
A frame synchronization protection circuit comprising an S-F/F circuit.