JPH0447345B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] Controls one channel of the direct memory access (hereinafter abbreviated as DMA) control circuit, synchronizes with the serial communication control circuit, and performs serial communication with the memory of transmit data and receive data in a time-sharing manner. By transferring data between control circuits, processor intervention is not required, and only one channel is required, increasing hardware resource utilization efficiency and eliminating limitations on the number of processor interrupt levels. .

[Industrial application field]

The present invention relates to a device that performs half-duplex communication using a DMA control circuit, and in particular, the DMA control circuit controls the serial communication control circuit, thereby reducing the burden on the processor and controlling the channel of the DMA control circuit. The present invention relates to a half-duplex communication method for direct memory access control circuits that also reduces the number of direct memory access control circuits.

In recent years, the operational format of computer systems has changed from host-centric to workstation-centric, and from centralized data processing to distributed processing, where workstations and host computers are connected by lines and Communication is becoming more and more popular.

For this reason, it is equipped with a processor, memory, DMA control circuit, and serial communication control circuit, and by controlling the channel of the DMA control circuit, data is sent from the memory to the line via the serial communication control circuit, and data is received from the line by the serial communication control circuit. Devices that transfer data using half-duplex communication by storing data in memory have come into use.

When performing such half-duplex communication, it is necessary to reduce processor intervention as much as possible, and to reduce the number of channels in the DMA control circuit.

[Conventional technology]

Figure 3 is a block diagram explaining the conventional technology.
FIG. 4 is a time chart explaining the operation of FIG. 3.

When processor 1 starts transmitting, it first
The DMA control circuit 2 is enabled and the serial communication control circuit 6 is instructed to start transmitting, and the serial communication control circuit 6 calls the other device via the line. When communication is possible, the communication starts as shown in FIGS. 3 and 4. , sends a transmission data transfer request to channel 3 of DMA control circuit 2. Channel 3 sends a bus occupancy request to processor 1 via the common part of DMA control circuit 2, occupies the bus, reads data from memory 5, and sends it to serial communication control circuit 6 as shown in FIG.

The serial communication control circuit 6 converts this parallel data into serial data and sends it to the line as shown in FIG. When the transmission is completed, as shown in FIGS. 3 and 4, a non-maskable interrupt is used to interrupt the processor 1 to notify the processor 1 of the completion of the transmission.

Processor 1, notified of the completion of transmission by this interrupt, sends out a signal to switch serial communication control circuit 6 from the transmission state to the reception state, as shown in FIG. When the serial communication control circuit 6 receives serial data from the other device, it converts it into parallel data.
As shown in FIGS. 3 and 4, a data transfer request is sent to channel 4 of DMA control circuit 2.

The channel 4 sends a bus occupancy request to the processor 1 via the common part of the DMA control circuit 2, and when the bus is occupied, the received data sent by the serial communication control circuit 6 is transferred to the memory 5 as shown in FIG. , are sequentially stored in the memory 5 as shown in FIG.

When the data reception is completed, the serial communication control circuit 6 notifies the processor 1 of the completion of reception by a non-maskable interrupt, as shown in FIGS. 3 and 4. Processor 1 receives this reception completion notification.
After disabling the DMA control circuit 2, it sends a signal to the serial communication control circuit 6 to switch the serial communication control circuit 6 to a reception disabled state, as shown in FIG.

Thereafter, the above operation is repeated after a specified period of time has elapsed.

When waiting for reception from a partner device, the processor 1 enables the DMA control circuit 2 and the serial communication control circuit 6. When called by the other device, the serial communication control circuit 6 notifies the processor 1 of data reception by a non-maskable interrupt, as shown in FIGS. 3 and 4. Processor 1, which was notified of data reception by this interrupt,
A signal is sent to switch the serial communication control circuit 6 to a receiving state. The subsequent operations are the same as those described above, so the explanation will be omitted.

[Problem that the invention seeks to solve]

As described above, conventionally, the serial communication control circuit 6 interrupts the processor 1 with a non-maskable interrupt to switch between the transmitting state and the receiving state according to instructions from the processor 1, and the channel 3 of the DMA control circuit 2 is used for transmit data transfer control, and channel 4 is used for receive data transfer control.

By the way, in half-duplex communication, transmission and reception are carried out in a time-division manner, so channel 4 is not operating during transmission, and channel 3 is not operating during reception. Therefore, there is a problem that the hardware is not used effectively.

Furthermore, the processor 1 must receive interrupts when a parity error occurs in the memory 5, interrupts from other input/output devices, etc., and must receive interrupts from the serial communication control circuit 6 as non-maskable interrupts to switch the transmit/receive state. If this occurs, important interrupt processing may be delayed, or
There are disadvantages such as inability to distinguish from errors, and a processor with three or more interrupt levels is required, while a processor with two interrupt levels is difficult to use.

[Means for solving problems]

FIG. 1 is a block diagram of a circuit showing one embodiment of the present invention.

The instruction decoding circuit 8 of the DMA control circuit 7 reads the instruction from the instruction table 9 of the memory 5 and analyzes it.
A transmission data transfer request sent by the serial communication control circuit 6 input via the channel 10 instructs the channel 10 to transmit the transmission data from the memory 5 to the serial communication control circuit 6, and when the transfer of a predetermined amount of data is completed. , reads the commands from the command table 9, switches the serial communication control circuit 6 to a receiving state, and stores the received data in the memory 5.

[Effect]

By having the above configuration, the DMA control circuit 7
The instruction decoding circuit 8 of the processor 1 analyzes the instructions in the instruction table 9 of the memory 5, and controls the channel 10 and the serial communication control circuit 6 in a time-sharing manner to transmit and receive data. It becomes possible to eliminate the need for transmission/reception switching control intervention in the circuit 6.

Therefore, only one channel 10 is required, which reduces the burden on the processor 1 and eliminates limitations on the number of interrupt levels of the processor 1.

〔Example〕

FIG. 2 is a time chart explaining the operation of FIG. 1.

In FIG. 1, processor 1 enables DMA control circuit 7 when starting transmission.
As a result, the instruction decoding circuit 8 of the DMA control circuit 7
reads the command from the command table 9 in the memory 5 via the channel 10, analyzes it, and enters a standby state.

After that, the processor 1 uses the serial communication control circuit 6.
The serial communication control circuit 6 calls the other device via the line, and when communication is possible, the OR circuit 1
1 and sends a transmission data transfer request to channel 10 of DMA control circuit 7.

The DMA control circuit 7, which has received a transmission data transfer request via the channel 10, sends a bus occupancy request to the processor 1, occupies the bus, and then causes the channel 10 to read data from the memory 5, as shown in FIG. It is sent to the serial communication control circuit 6.

The command table 9 is set in a predetermined format to instruct transmission data transfer, switching of the serial communication control device 6 to the reception state, and reception data transfer.

The serial communication control circuit 6 converts the parallel data read from the memory 5 into serial data and converts it into serial data.
It is sent to the line as shown in . When the predetermined amount of data has been transferred, the instruction decoding circuit 8 reads the next instruction from the instruction table 9 in the memory 5 via the channel 10.

Since the next command in the command table 9 instructs the serial communication control circuit 6 to switch to the receiving state, the channel 10, as shown in FIG. A signal is sent to switch the serial communication control circuit 6 to a receiving state.

Thereafter, the instruction decoding circuit 8 reads the next instruction from the instruction table 9 in the memory 5, analyzes it, and enters a standby state.

When the serial communication control circuit 6 receives data from the other device, it converts it into parallel data and sends it to the OR circuit 1.
1, a data transfer request is sent to the channel 10 as shown in FIGS. 1 and 2.

The DMA control circuit 7, which has received this data transfer request via the channel 10, sends a bus occupation request to the processor 1, and when the bus is occupied, the DMA control circuit 7
0 to transfer received data. The channel 10 transfers the received data sent by the serial communication control circuit 6 to the memory 5 as shown in FIG.
The data are sequentially stored in the memory 5 as shown in FIG.

When the reception of data is completed, the serial communication control circuit 6 notifies the processor 1 of the completion of reception by means of a maskable interrupt via the interrupt control circuit 12, as shown in FIGS. 1 and 2. Processor 1 stops DMA control circuit 7 and disables serial communication control circuit 6.

This completes one transmission/reception operation, and the above operation is repeated thereafter.

When waiting for reception from the other device, the processor 1 sends the instruction table 9 to the DMA control circuit 7 in advance.
It is instructed to operate from the received command. The command decoding circuit 8 starts reading from the received data transfer command in the command table 9, and sends out a signal to switch the serial communication control circuit 6 to the receiving state via the channel 10.

When called by a partner device, the serial communication control circuit 6 sends a data transfer request to the channel 10, as shown in FIG. The DMA control circuit 7, which has been requested to transfer data via the channel 10, occupies the bus and instructs the channel 10 to transfer the received data, as described above. The subsequent operations are the same as those described above, so the explanation will be omitted.

〔Effect of the invention〕

As explained above, the present invention switches one channel of the DMA control circuit in a time-division manner to control data transfer in half-duplex communication, which makes it possible to effectively utilize hardware resources, and also allows the serial communication control circuit to control data transfer. Since the processor does not need to intervene in the transmission/reception state switching control, the burden on the processor can be reduced and the limit on the number of interrupt levels can be eliminated.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a circuit showing an embodiment of the present invention, FIG. 2 is a time chart explaining the operation of FIG. 1, FIG. 3 is a block diagram explaining a conventional technique, and FIG. 3 is a time chart explaining the operation of FIG. 3. In the figure, 1 is a processor, 2 and 7 are DMA
Control circuits, 3, 4, and 10 are channels, 5 is a memory, 6 is a serial communication control circuit, 8 is an instruction decoding circuit, 9 is an instruction table, 11 is an OR circuit, and 12 is an interrupt control circuit.

Claims (1)

[Scope of Claims] 1. A device that performs half-duplex communication by comprising a processor 1, a direct memory access control circuit 7 having a plurality of channels, a memory 5, and a serial communication control circuit 6, wherein the memory 5 has the serial communication control circuit 7. an instruction table 9 storing instructions in a predetermined order for instructing the circuit 6 to switch the transmission/reception state and transfer data; and the direct memory access control circuit 7 is provided with an instruction decoding circuit 8 for decoding the instructions in the instruction table 9. The command decoding circuit 8 controls one channel 10 of the direct memory access control circuit 7 based on the command read from the command table 9 and the data transfer request from the serial communication control circuit 6, and reads the command in a time-sharing manner. A half-duplex communication system for a direct memory access control circuit, characterized in that transmission data and reception data are transferred between the memory 5 and the serial communication control circuit 6 in synchronization with the serial communication control circuit 6.