JPS63149751A - Half-duplex communication system in direct memory access control circuit - Google Patents

Abstract

PURPOSE:To reduce the load on a processor and to remove the restriction to the number of interruption levels by switching one channel in a direct memory access (DMA) control circuit on time-division basis and controlling data transfer of half-duplex communication. CONSTITUTION:An instruction decoding circuit 8 in the DMA control circuit 7 reads out and analyzes an instruction from an instruction table 9 in a memory 5, instructs a channel 10 based on a transmission data transfer request sent from a serial communication control circuit 6 and inputted through the channel 10 to send transmission data from the memory 5 to the circuit 6, and after completing the transfer of the prescribed volume of data, reads out an instruction from an instruction table 9, switches the circuit 6 to a receiving state, and stores the received data in the memory 5. Consequently, a processor 1 can be allowed to omit transmission/reception switching control for the circuit 6. Thereby, only one channel may be used, the load on the processor 1 can be reduced and the restriction to the number of interruption levels in the processor 1 can be eliminated.

Description

[Detailed Description of the Invention] [Summary] Controls one channel of a direct memory access (hereinafter abbreviated as DMA) control circuit, synchronizes with a serial communication control circuit,
By time-divisioning data transfer between the memory for transmit data and receive data and the serial communication control circuit, processor intervention is not required, and only one channel is required, making the use of hardware resources more efficient. and eliminated the limit on the number of processor interrupt levels.

[Industrial application field]

The present invention relates to a device that performs half-duplex communication using a DMA control circuit, and in particular, the DMA control circuit controls a serial communication control circuit, thereby reducing the burden on a processor and improving DMA Sli control. The present invention relates to a half-duplex communication method for direct memory access control circuits that also reduces the number of channels in the circuit.

In recent years, the operating format of computer systems has changed from host-centric to workstation-centric, and from centralized data processing to distributed processing, where workstations and host computers are connected by lines and are interconnected. communication has become popular.

For this purpose, it is equipped with a processor, a memory, a DMA control circuit, and a serial communication control circuit, and by controlling the channel of the DMA control circuit, data is sent from the memory to the line via the serial communication control circuit, and data is received from the line by the serial communication control circuit. Devices that transfer data using half-duplex communication have come into use by storing the data in memory.

When performing such half-duplex communication, it is necessary to reduce processor intervention as much as possible and to reduce the number of channels of the DMA control circuit.

[Prior Art] FIG. 3 is a block diagram illustrating the conventional technique, and FIG. 4 is a time chart illustrating the operation of FIG. 3.

When the processor 1 starts transmission, it first enables the DMA control circuit 2 and instructs the serial communication control circuit 6 to start transmission.The serial communication control circuit 6 calls the other device via the line, and when communication becomes possible, As shown in FIGS. 3 and 4, a transmission data transfer request is sent to channel 3 of the DMA control circuit 2. Channel 3 sends a bus occupancy request to processor 1 via the common part of DMA control circuit 2, occupies the bus, reads data from memory 5, and sends it to serial communication control circuit 6 as shown in FIG. .

The serial communication control circuit 6 converts this parallel data into serial data and sends it to the line as shown in FIG. When the transmission is completed, as shown in Figures 3 and 4,
A non-maskable interrupt notifies processor l of transmission completion.

The processor 1, notified of the completion of transmission by this interrupt, sends out a signal to switch the serial communication control circuit 6 from the transmission state to the reception state, as shown in FIG. When the serial communication control circuit 6 receives serial data from the other device, it converts it into parallel data and converts it into parallel data as shown in FIGS. 3 and 4.
A data transfer request is sent to channel 4 of MA control circuit 2.

Channel 4 sends a bus occupation request to processor 1 through the common part of DMA'H) control circuit 2, and when the bus is occupied, the serial communication control circuit 6 sends out received data as shown in FIG. are transferred to the memory 5 and sequentially stored in the memory 5 as shown in FIG.

When the data reception is completed, the serial communication control circuit 6 notifies the processor 1 of the reception completion by a non-maskable interrupt as shown in FIGS. 3 and 4. After disabling the control circuit 2, a signal is sent to the serial communication control circuit 6 to switch the serial communication control circuit 6 to a reception disabled state, as shown in FIG. 4 [phase].

Thereafter, the above operation is repeated after a specified period of time has elapsed.

When waiting for reception from the partner device, the processor 1 enables the DMA control circuit 2 and the serial communication control circuit 6. When the serial communication control circuit 6 is called by the partner device, As shown in FIG. The operation is the same as above, so the explanation will be omitted.

[Problem that the invention seeks to solve]

As mentioned above, conventionally, the serial communication control circuit 6 interrupts the processor 1 with a non-maskable interrupt to switch between the transmission state and the reception state according to instructions from the processor 1, and the channel of the DMA control circuit 2 Channel 3 is used to control transmission data transfer, and channel 4 is used to control reception data transfer.

By the way, in half-duplex communication, transmission and reception are carried out in a time-division manner, so channel 4 is not operating during transmission, and channel 3 is not operating during reception. Therefore, there is a problem that the hardware is not used effectively.

Furthermore, the processor 1 must receive interrupts from the parity error of the memory 5 and other input/output devices, and must receive interrupts from the serial communication control circuit 6 as non-maskable interrupts for switching between transmission and reception states. This causes problems such as delays in important interrupt processing and inability to distinguish them from errors, which requires a processor with 3 or more interrupt levels, making it difficult to use a processor with 2 interrupt levels. There's a problem.

[Means for solving problems]

FIG. 1 is a block diagram of a circuit showing one embodiment of the present invention.

The command decoding circuit 8 of the DMA control circuit 7 reads the command from the command table 9 of the memory 5, analyzes it, and instructs the channel 10 by the transmission data transfer request sent by the manually operated serial communication control circuit 6 via the channel 10. memory 5
sends the transmission data from to the serial communication control circuit 6,
When the transfer of a predetermined amount of data is completed, the command from the command table 9 is read out, the serial communication control circuit 6 is switched to the receiving state, and the received data is stored in the memo '15.

[Effect]

With the above configuration, the instruction decoding circuit 8 of the DMA control circuit 7 analyzes the instructions in the instruction table 9 of the memory 5,
Since the channel IO and the serial communication control circuit 6 are controlled in a time-sharing manner to transmit and receive data, it is possible to eliminate the need for the processor 1 to intervene in the transmission/reception switching control for the serial communication control circuit 6.

Therefore, only one channel 10 is required, which reduces the burden on the processor 1 and eliminates limitations on the number of interrupt levels of the processor 1.

〔Example〕

FIG. 2 is a time chart explaining the operation of FIG. 1.

In FIG. 1, when processor 1 starts transmitting,
Enable the DMA #J control circuit 7.

As a result, the instruction decoding circuit 8 of the DMA f;11 control circuit 7 reads the instruction table 9 of the memory 5 via the channel 10.
It reads out the command from the computer, analyzes it, and enters a standby state.

After that, the processor 1 instructs the serial communication control circuit 6 to start transmission, and the serial communication control circuit 6 calls the other party's device via the line, and when communication becomes possible, as shown in FIGS. 1 and 2 (◎). A transmission data transfer request is sent to channel 10 of DMA control circuit 7 via OR circuit 11.

DMA receives transmission data transfer request via channel 10
The control circuit 7 sends a bus occupancy request to the processor 1, occupies the bus, and then causes the channel IO to read data from the memory 5 and send it to the serial communication control circuit 6 as shown in FIG.

In the command table 9, in a predetermined format, there are instructions for transmitting data transfer, switching the serial communication control device 6 to the receiving state, and
It is set to command receive data transfer.

The serial communication control circuit 6 converts the parallel data read from the memory 5 into serial data and sends it to the line as shown in FIG. When the predetermined amount of data has been transferred, the instruction decoding circuit 8 reads the next instruction from the instruction table 9 of the memory 5 via the channel 10.

Since the next command in the command table 9 instructs the serial communication control circuit 6 to switch to the receiving state, the command decoding circuit 8 that decoded this command commands the channel 10 as shown in FIG. A signal is sent to switch the serial communication control circuit 6 to a receiving state.

Thereafter, the instruction decoding circuit 8 reads the next instruction from the instruction table 9 in the memory 5, analyzes it, and enters a standby state.

When the serial communication control circuit 6 receives data from the partner device, it converts it into parallel data, and sends a data transfer request to the channel 10 via the OR circuit 11, as shown in FIGS. 1 and 2 (2).

DMA that received this data transfer request via channel 10
The control circuit 7 sends a bus occupancy request to the processor 1, and when the bus is occupied, it instructs the channel 10 to transfer the received data. The channel IO transfers the received data sent out by the serial communication control circuit 6 to the memory 5 as shown in FIG. 2 [phase], and sequentially stores it in the memory 5 as shown in FIG. 2O.

When the data reception is completed, the serial communication control circuit 6 notifies the processor 1 of the completion of reception by a maskable interrupt via the interrupt control circuit 12, as shown in FIGS. 1 and 2 [phase]. Processor 1 is DMA control circuit 7
, and the serial communication control circuit 6 is disabled.

This completes - times of transmission/reception operations, and the above operations are repeated thereafter.

When waiting for reception from a partner device, the processor 1 instructs the DMA control circuit 7 in advance to operate from the reception command in the command table 9. The instruction decoding circuit 8 starts reading from the received data transfer instruction in the instruction table 9,
A signal is sent via channel 10 to switch serial communication control circuit 6 to a receiving state.

When the serial communication control circuit 6 is called by the other device,
As shown in FIG. 2 [phase], a data transfer request is sent to the channel 10. DMA requested to transfer data via channel 10! Similarly to the above, the II control circuit 7 occupies the bus and instructs the channel 10 to transfer received data. The subsequent operations are the same as those described above, so the explanation will be omitted.

〔Effect of the invention〕

As explained above, the present invention switches one channel of the DMA control circuit in a time-division manner to control data transfer in half-duplex communication, which makes it possible to effectively utilize hardware resources, and also to improve the efficiency of the serial communication control circuit. Since processor intervention is not required for transmission/reception state switching control, the burden on the processor can be reduced and limitations on the number of interrupt levels can be eliminated.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a circuit showing one embodiment of the present invention, FIG. 2 is a time chart explaining the operation of FIG. 1, and FIG.
The figure is a block diagram explaining the conventional technique, and FIG. 4 is a time chart explaining the operation of FIG. 3. In the figure, 1 is a processor, 2 and 7 are DMA control circuits, and 3
．． 4.10 is a channel, 5 is a memory, 6 is a serial communication control circuit, 8 is an instruction decoding circuit, 9 is an instruction table, 11 is an OR circuit, and 12 is an interrupt control circuit. Column ε1 圀0) Tsuka Keya Torch Explained with Captive Kauta 2
2

Claims (1)

[Claims] An apparatus for performing half-duplex communication comprising a processor (1), a direct memory access control circuit (7) having a plurality of channels, a memory (5), and a serial communication control circuit (6), comprising: an instruction table (9) storing instructions in a predetermined order instructing the serial communication control circuit (6) to switch the transmission/reception state and transfer data in the memory (5); An instruction decoding circuit (8) for decoding the instructions in the table (9) is provided, and the instruction decoding circuit (8) reads out the instructions from the instruction table (9) and data from the serial communication control circuit (6). Based on the transfer request, one channel (10) of the direct memory access control circuit (7) is controlled, and in synchronization with the serial communication control circuit (6) on a time-sharing basis, the memory (
5) and the serial communication control circuit (6), the half-duplex communication method for the direct memory access control circuit is characterized in that data transfer of transmission data and reception data is performed between the serial communication control circuit (6) and the serial communication control circuit (6).