JPH0447565A - Digital signal recording and reproducing system - Google Patents

Abstract

PURPOSE:To make coincidence of the timing for reproducing a picture and a sound by starting recording an audio signal after recording a picture data of an odd field at the time of recording and processing a time axis changeover when the picture data of the odd field is written in a memory at the time of starting reproducing. CONSTITUTION:A digital video signal which is separated by a separating means 36 from a digital signal to be reproduced is changed in time axis and outputted by memories 62 and 64. At the time of starting recording, a digital audio signal which is supplied to terminals 8L and 8R is recorded after recording the last picture data of an odd field out of a picture digital data of one frame. Moreover, at the time of starting reproducing, a picture data of an odd field is repeatedly read out of the memories for a period of time from that the last picture data of an odd field out of a picture data by one frame is written in the memories 62 and 64 to that the last picture data of an even field is written, and afterward, a picture data by one frame is repeatedly read out. By this method, the timing for reproducing a sound and a picture is thus coincident.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a recording and reproducing method for simultaneously recording and reproducing audio signals and video signals.

[Prior art] Current digital audio recorder (hereinafter referred to as rD)
(referred to as "AT") is designed to record and reproduce only audio signals.

However, since it would be very convenient to record and play back not only audio signals but also other signals, such as video signals for still images, the applicant first synthesized digital audio signals and digital video signals. , proposed simultaneous recording and playback.

[HIM problem that the invention aims to solve] By the way, the sampling frequency of the video signal is higher than the sampling frequency of the audio signal, and the time axis of the digital video signal is converted during recording and combined with the digital audio signal. The time axis of the signal is inverted.

The digital video signal has one of the odd and even fields.
When recording in units of frame image data,
The video signal is of the NTSC system, the video sampling clock is 4 f sc (f sc is the subcarrier frequency), and the audio sampling clock is 48 KH.
z, it takes about 5 seconds to record and reproduce one frame of image data.

If, during playback, one frame of image data is written to memory and then time axis conversion processing (reading processing using a different clock than that used during writing) is performed, the digital audio signal and digital video signal are When recording from the same timing, the image is played back approximately 5 seconds after the sound is played (Figure 7A,
(See B).

In other words, the playback timings of audio and images are significantly different.

Therefore, in the present invention, the playback timings of audio and images are made to match.

[! ! [Means for solving the problem] Synthesize an N-bit (N is an integer) digital audio signal and an M-bit (M is an integer) digital video signal that has been time-base converted using memory to create an N+M-bit digital signal. The recorded digital video signal is recorded in units of image data for one frame of odd and even fields, and the digital video signal separated from the N0M bit digital signal to be reproduced is subjected to time axis conversion in memory. and output.

Furthermore, at the start of recording, the final image data of an odd field of one frame of image data is recorded, and then the digital audio signal is recorded.

Furthermore, at the start of playback, from the time the final image data of the odd field of one frame of image data is written to the memory until the final image data of the even field is written, the image data of the odd field is repeatedly transferred from the memory. After that, one frame worth of image data is repeatedly read out from the memory.

[Operation] In the above configuration, the time axis conversion process is performed from the time when the final image data of the odd field is written into the memory constituting the time axis conversion means at the start of reproduction. For example 1
When the recording/reproducing time for a frame's worth of image data is approximately 5 seconds, the image is reproduced approximately 2.5 seconds after the first image data is written into the memory.

Furthermore, in the above configuration, at the start of recording S, the digital audio signal is recorded after the final image data of an odd field of one frame of image data is recorded. That is, for example, when the recording/reproducing time for one frame of image data is approximately 5 seconds, recording of the digital audio signal is started approximately 2.5 seconds later than the digital video signal.

Through such processing during recording and playback, the playback timings of audio and image coincide.

[Actual kPA] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

In this example, the analog audio signal is 1 sample 1
0-bit digital audio signal DSa [A9 to A
O] (shown in the 21st!IA) and further converts one sample 8-bit digital audio signal DSa'
[A? '~AO' ] (same 1!
(Illustrated in IB).

Further, the analog video signal is converted into a digital audio signal DSv[V7 to vO] of 8 bits per sample (as shown in C in the figure).

The second diagram shows the format of the digital signal DS recorded and reproduced in this example.

Of the 16-bit data DI5 to DO, the upper 8 bits contain a digital audio signal DSa' [A? '〜
An'] is allocated, and a digital video signal DSv[V7 to VO] is allocated to the lower 8 bits.

The digital signal DS having such a bit configuration is supplied to a rotating magnetic head (not shown) provided on the DAT, is recorded on a magnetic tape, and is reproduced from the magnetic tape.

As will be described later, in the DAT, both the left (L) channel and right (R) channel digital audio signals DSa sampled at the clock fs are sequentially recorded. Therefore, each sample data of the digital video signal DSv is mixed with the digital audio signal DSa and recorded in synchronization with the clock 2fs.

48kHz as audio sampling clock fs
When using , the video sampling clock is 4fsc
(In the case of the NTSC system, fsc is 3.58 MHz), there is a frequency difference of about 149 times between the video sampling clock 4fsc and the above-mentioned clock 2fs. In other words, each sample data of the digital video signal DSv sampled at a period of I/4 fsc is 1/2 fs (149 of 1/4 fsc).
data is recorded sequentially at a period of about twice as long.

Therefore, since one frame period is 1730 seconds, 1
It will take approximately 4.96 seconds to record a frame (odd field F and even field) of video signal. Furthermore, as will be described later, since an identification code ID is added to the video signal, it takes approximately 5 seconds for one frame of the video signal to be finally recorded.

FIG. 3 is a diagram showing the data structure. In other words, ltm
Odd numbers (ODD) and even numbers (EVEN) that make up the i-plane
Immediately before the video signal of each field is a start code S•ID indicating the start of data.

A moat code MD-ID% for distinguishing between an odd field and an even field and a last start coat LS/rD for distinguishing between an identification code and data are added. Further, a stop code E/ID indicating the end of data is added immediately after the video signal of each field.

For example, the start code S-ID is composed of 8-bit data in which only the least significant bit is "l", and the stop code E-ID is composed of 8-bit data in which all bits are "o".

FIG. 1 shows an example of a signal processing device for forming a digital signal DS in the format shown in FIG. 2 and recording and reproducing it on a DAT with the data structure shown in FIG.

First, a signal processing system for audio signals will be explained.

Left and right channel audio signals SaL% supplied to audio in terminals 8L and 8R SaR is amplifier 9L,
Amplified by 9R, noise reduction #il O
Noise is removed by L, IOR, and low-pass filter II
Bandwidth is limited by L and IIR.

Then, it is supplied to the A/D converters 12L and 12H.
Bit digital audio signals DSaL, DSaR
is converted to Audio sampling clock fs (48kHz2) is used for A/D conversion 1112L and 12R.
is supplied.

Digital audio signals DSaL% DSaR output from the A/D converters 12L and 12R are supplied to Lll and R@ of the changeover switch 13, respectively.

A clock LRCK with a frequency of 48kHz and a duty of 50% is supplied to this changeover switch 13, and a clock LRCK with a frequency of 48kHz and a duty of 50% is supplied,
It is alternately switched to the R side and the R side every cycle of z.

The digital audio signal DSa output from the changeover switch 13 is supplied to a compression circuit 14, where it is converted from a 1-sample 10-bit signal to a 1-sample 8-bit signal.

The digital audio signal DSa' converted into an 8-bit signal by the compression circuit 14 is supplied to a mixing means (adder) 20 constituting the mixing/separating means 86 and mixed with a digital video signal DSv, which will be described later. The mixed digital signal DS (shown in the second diagram) is then supplied to the digital out processing circuit 22, where it is converted into a digital signal conforming to the DAT audio format.

As is well known, the digital out processing circuit g122 is provided with clock generation means for generating the pit clock BCK.

The formatted digital signal DS is finally supplied to the rotating magnetic head (not shown) of the DAT via the digital out terminal 24 and recorded thereon.

The digital signal DS reproduced by the rotating magnetic head is supplied to the digital input processing circuit 1a34 via the digital input terminal 32, and is subjected to digital input processing 6. For example, a PLL circuit (not shown) is driven to generate a reproduction pit. A master clock synchronized with clock BCK is generated.

A separation signal for separating the digital audio signal DSa and the digital video signal DSv is generated based on this master clock, and the next-stage separation means 36 outputs the digital audio signal DSa' (shown in FIG. 2B) and the digital The video signal DSv (shown in C of the same figure) is separated and output.

The 8-bit digital audio signal DSa' separated every 1/96 kHz by the separation means 36 is supplied to an expansion circuit 38. In this expansion circuit 38,
The digital audio signal DSa, which has been converted into an lθ bit signal by the decompression circuit 38, undergoes processing opposite to that of the compression circuit 14, and the 1 sample 8 bit signal is returned to the 1 sample 10 bit signal. 39 movable terminals. A clock LRCK is supplied to this changeover switch 39, and the changeover switch 39 is alternately switched to the L side and R11 at every 1/96 kHz cycle. In other words, the fixed terminals on the L side and R side of the changeover switch 39 each have a 1/2
Even with a frequency of 48 kHz, left and right channel digital audio DSaL and DSaR can be obtained.

The digital audio DSaL and DSaR output from the changeover switch 39 are D/A converters 114OL.

It is supplied to 4OR and converted into an analog signal.

;-(DA/DA/D converter 540LR4m!, t, audio sampling clock fs is supplied.

The audio signals S and SaR output from the D/A converters 1140L and 4OR are passed through low-pass filters 41L and 41.
The band is limited by R, and the noise reduction circuit 42L, 4
After the noise is removed with 2R, further amplifier 43L,
Amplified by 43R and audio out terminals 44L, 4
Output on 4H.

Next, a signal processing system for video signals will be explained.

The still image video signal Sv supplied to the video in terminal 60 is amplified by the amplifier δ2, and then A/D converted W5.
4, and one sample is converted into an 8-bit digital signal. This A/D conversion 1t54 has 4 fs
c (f sc is the subcarrier frequency, 3.58
MHz) sampling clock is used.

The digital video signal DSv output from the A/D converter W54 is supplied to the all fixed terminal of a changeover switch 66 that switches between a human input signal and a reproduction signal. The output signal of this changeover switch 56 is supplied to memories 62 and 64 constituting the memory means 60 as a write signal.

The memories 62 and 64 each have a storage capacity for one frame. Writing and reading of these memories 62 and 64 are controlled by a controller 100 having a CPU supplying ms times signals to memory control circuits vIi 70 and 72.

The video signal Sv supplied to the terminal 50 is supplied to the subcarrier extraction circuit 110 via the amplifier 52, and the subcarrier fsc extracted at this extraction time N110 is supplied to the controller 100.

Further, the digital video signal DSv output from the A/D converter 54 is supplied to the vertical synchronization separation circuit 112,
The vertical synchronization signal separated by this separation circuit 112 is supplied to the controller 100. The memory control circuits 70 and 72 include subcarrier fsc, vertical synchronization signal,
A control signal is supplied based on the bit clock BCK.

In this case, during recording, writing to the memories 62 and 64 is performed with a clock of 4 fsc, and reading is performed with a clock of 2 fsc to one memory, and a clock of 2 fsc to the other memory. then 4
This is done using the fsc clock. That is, one memory functions as a time axis compression means for the digital video signal DSv because it combines the digital video signal DSv with the above-mentioned digital audio signal DSa.

Also, during playback, writing to the memories 62 and 64 is performed using a clock with a frequency of 2fs, and
The reading is performed with a clock of 4fSC. In other words, the memories 62 and 64 function as time axis expansion means for the digital video signal DSv.

The signal read from the memory 62 is transferred to the selector switch 66.
．． The signal supplied to the e@ fixed terminal of 68 and read from the memory 64 is supplied to the fll fixed terminal of changeover switches 66 and 68. These changeover switches 66.68
The switching is controlled by the controller 100.

The digital video signal DSv output from the changeover switch 68 is supplied to a sync bit shift encoder 76, where a sync bit shift process is performed.

Originally, a video signal is A/D converted into 8 bits, so its sync bits are digital data in which all bits are "0". However, since the identification code ID is assigned to a bit that does not affect the image as described above, the encoder 76 shifts the sync bit by one bit so that the identification code ID and the sync bit can be distinguished. (See Figure 4 N).

The digital video signal DSv on which the sync bits have been shifted by the encoder 76 is supplied to an adder 78, where an identification code ID is added (3rd book Pi). It is a generator.

The digital video signal DSv to which the identification code ID has been added by the adder 78 is subjected to parallel-to-serial conversion processing in the signal processing circuit 82, and bit inversion processing is also performed on the most significant bit MSB of the digital video signal DSv. This process will be described later.

The digital video signal DSv, which has undergone predetermined signal processing in the signal processing circuit 82, is mixed with the digital audio signal DSa' by the mixing means 20, as shown in the second diagram, and sent to DATll.

Furthermore, when reproducing the digital signal DS, the separating means 36
The digital video signal DSv separated by is subjected to serial/parallel conversion processing in the signal processing circuit 90, and at the same time, the most significant bit MSB of the digital video signal DSv is inverted.

Then, in the sync bit shift decoder 92, only the sync bits are shifted in the opposite manner to that during recording, and after returning to the original sync bits (see the fourth book wl), the changeover switch 5
It is supplied to the fixed terminal on the b side of 6.

Switching of the changeover switch 56 is controlled by the controller 100, and is connected to the a side during recording, and connected to bs during playback.

Further, the digital video signal DSv output from the changeover switch 66 is supplied to the fixed terminal on the g side of the changeover switch 102, and the fixed terminal on the h side is connected to the A/D converter l154.
output signal is provided. This switching of the changeover switch 102 is controlled by the controller 100. In other words, when displaying a moving image (through image) during recording, h
When displaying still images that are connected to the side and recorded, use ge.
connected to l. During playback, it remains connected to g@.

The digital video signal DSv outputted from the changeover switch 102 is converted into an analog signal by the D/A conversion III 04, and then outputted to the video out terminal 108 via the amplifier 106. A monitor means (rl!j, O not shown) is connected to this terminal 108.

Further, the output signal of the signal processing circuit 90 is the identification code F detection W.
94. The identification code 10 detected by the detector 94 is supplied to the controller 100. Based on this identification code ID, the memory control circuit 70.72
is controlled.

During playback, when the digital video signal DSv to which the identification code ID is added is played back and stored in the memory means 60, only image data is stored.

At that time, in both odd and even fields,
The final data is obtained when a predetermined period of time has elapsed since the first data of the image data.In order to detect this final data more accurately, in addition to time-based management, a stop code E.
When the ID is detected and the two match, it is determined as the final image data. Then, when the writing of the final image data of the even field is completed, the memory 62.64
At the same time, the write and read modes are reversed, and the changeover switches 66 and 68 are also switched to the opposite side.

By the way, during the reproduction of the digital video signal DSv, the DA
When the reproduction of T is stopped, all bits of the reproduced output data supplied to the terminal 32 become "0" as shown in FIG.

Since time management (count-up processing) for image data is performed on the signal processing device side shown in FIG.
Even if the reproduction of T is stopped, the count-up process does not stop in conjunction with this.

Therefore, one memory of the memory means 60, for example the memory 64, remains in the write state and all bits are
0'' data is written as original image data.

When a predetermined period of time has elapsed from the stop mode of the DAT, it is time to play back the final image data of the even field, and all bits of the playback data at that time are always "0", so this is used as a stop code. Misjudged as E-ID. As a result, the signal processing device considers that the final image data has arrived, and switches the changeover switch 66.6.
8 is switched, and the memory 64 is controlled to read mode.

Then, after DAT goes into stop mode, memory 6
Since all the bits "0" data written in 4 is read out and displayed as a black image, a very unsightly image will be displayed on the monitor.

To avoid this, if the most significant bit of the image data is inverted and recorded as described above and then inverted again during playback, the 51st!
As shown in I, even if all bits of the reproduced output data at the time of a mid-stop are "0", the most significant bit MSB becomes "1" when re-inversion processing is performed.

As a result, the signal processing device side does not judge that the final screen data has arrived, and the memory means 60 does not perform switching control, so the previous screen is always monitored, and the above-mentioned drawbacks are eliminated. .

In addition, the controller]00 has a shutter switch 5.
WSH1 Record switch 5WRE, Playback switch 5WPL
, pause switch 5WPA, stop switch 5WST
and a recording mode selection switch SWMO are connected.

When the playback switch 5WPL is turned on, it is the time of playback. As a result, the DAT is placed in a playback state, and
The changeover switch 56 is connected to the b side.

The reproduced digital video signal DSv is written into one of the memories 62 and 64 via the changeover switch 56 with a clock of 2 fs. While being written to one of the memories 62.64, one frame worth of digital video signal DSv is repeatedly read out from the other memory with a clock of 4 fsc, and the changeover switch 66.10
After the signal is supplied to the D/A converter 104 through 2 and converted into an analog signal, it is supplied to a monitor to display a still image.

When one field's worth of final image data is written into one memory, the write/read modes of the memories 62 and 64 are reversed, and the selector switch 66 is also switched.

As a result, the reproduced digital video signal DSv is now written to the other memory with a clock of 2 fs, and one frame worth of digital video signal DSv is repeatedly read out from one memory with a clock of 4 f sc. A still image is displayed on the monitor.

Thereafter, reading and writing to and from the memories 62 and 64 are repeated as described above.

Next, when the recording switch 5WRE is turned on, it is the recording time. As a result, the DAT is placed in a recording state, and the changeover switch 56 is connected to all.

At the time of this recording, the mote selection switch SWMO is
Each S side, ml! When connected to side A, one-shot mode, manual mode, and auto mode are selected.

In one-shot mode, shutter switch 5WSN
By turning on, one frame of image data is captured in the memory and this image data is recorded only once - automatically entering a recording pause state.

In the manual mode, by turning on the shutter switch 5WSH, one frame of Ii image data is captured into the memory, and this image data is recorded one or more times. To record the same image data any number of times until a recording pause state or stop state is reached.

In auto mode, the shutter is automatically turned on and
One frame of image data is taken into memory and this image data is recorded. When recording is completed, the shutter is automatically turned on again, one frame worth of image data is captured in the memory, and this image data is recorded. This is repeated until the recording pause state or stop state is reached.

Next, details of the recording operation will be explained using the flowchart of FIG. 6.

When the recording switch 5WRE is turned on, step 101
The recording pause is automatically turned on.

At this time, the changeover switch 56 is connected to the a side, and the A/D
The digital video signal DSv from the converter 54 is transferred to the memory 62.6 of the memory means 60 via the changeover switch 56.
4 as a write signal. Also, at this time, the changeover switch 102 is connected to the A/D conversion@54
The digital video signal DSν from the selector switch 10
A monitor (not shown) that is supplied to the D/A converter 104 via 2 and connected to the video out terminal 108 includes:
A moving image (through m) based on the video signal Sv supplied to the video-in terminal 50 is displayed.

Next, in step 102, it is determined whether the mode is one-shot mode.

When the mode selection switch SWMO is connected to sl and the mode is one-shot mode, it is determined in step 103 whether the shutter switch 5WSH is on. Although not mentioned above, it is assumed that the shutter switch 5WSH automatically returns to OFF.

When the shutter switch 5WSH is on in step 103, one frame worth of video data DSv is written in the memory 62, 64 with a clock of 4 fsc in step 104.

Next, in step 105, one frame of video data DSv is repeatedly read out from the memory 62 with a clock of 4 fSC. At this time, the changeover switch 102
is switched from the h side to g@, so the l frame worth of video data DSv read from the memory 62 is converted to D/A 1104 via the changeover switch 66.102.
A still image is displayed on the monitor connected to the terminal 108.

Next, in step 106, it is determined whether the pause switch 5WPA is off. When it is not off, the process returns to step 103; when it is off, the process returns to step 10.
At step 7, one frame of video data DSv is read from the memory 64 with a clock of 2 fs, and when the selector switch 68 is turned on, this is mixed with the digital audio signal DSa' and recorded as DAT as described above.

Next, in step 108, it is determined whether recording is complete. When recording of video data DSV for one frame is completed, the recording pause is automatically turned on in step 109.

Then, in step 110, the selector switch 1゜2 is set to h
A moving image (through Ii) based on the video signal Sv supplied to the video out terminal 50 is displayed on the monitor connected to the video out terminal 108, and the process returns to step 103.

Also, in step 103, the shutter switch 5WSH
When is off, it is determined in step 111 whether or not a through image is being displayed on the monitor. If a still image is displayed instead of a through image, step 105
When the through image is being displayed, it is determined in step 112 whether the pause switch 5WPA is off.

If it is not off, the process returns to step 103. When it is off, in step 113, a still image is displayed on the monitor in the same manner as in step 105, and the process proceeds to step 107.

Further, if it is determined in step 102 that the mode is not one-shot mode, it is determined in step 115 whether or not the mode is manual mode.

When the mode selection switch SWMO is connected to the m side and the mode is manual mode, it is determined in step 116 whether the shutter switch 5WSH is on.

When the shutter switch 5WSH is on, one frame of video data DSv is written in the memory 62, 64 of the memory means 60 in step 117.

Next, in step 118, a still image is displayed on the monitor in the same manner as in step 105. And step 11
At step 9, it is determined whether the pause switch 5WPA is off. If it is not off, the process returns to step 116.

When it is off, one frame of video data DSv is read out from the memory 64 in the same manner as in step 107, mixed with the digital audio signal DSa', and recorded as DAT.

Next, in step 121, it is determined whether recording is complete. When recording is completed, it is determined in step 122 whether the pause switch 5WPA is on. If it is not on, the process returns to step 118. When it is on, a through image is displayed on the monitor in step 123 in the same way as step 110, and step 116 is performed.
Return to

If the shutter switch 5WSH is not on in step 116, it is determined in step 124 whether or not a through image is being displayed on the monitor.

If a still image is being displayed instead of a through image, the process advances to step 118. If a through image is being displayed, it is determined in step 125 whether the pause switch 5WPA is off. If it is not off, the process returns to step 116. When it is off, a still image is displayed on the monitor in step 126 in the same manner as in step 105, and the process proceeds to step 120.

Further, if it is determined in step 115 that the mode is not one-shot mode, it is determined in step 128 whether or not the mode is auto mode.

When the mode selection switch SWMO is connected to the a side and the mode is in auto mode, it is determined in step 129 whether the pause switch SWP^ is off. When it is off, in step 130 the controller 100
After the internal shutter is turned on, step 13
1, one frame of video data DSv is written into the memories 62 and 64 of the memory means 60.

Next, in step 132, a still image is displayed on the monitor in the same manner as in step 105. And step 13
3, in the same way as step 107, 1 is read from the memory 64.
Frame worth of video data DSV is read out, mixed with digital audio signal DSa', and recorded as DAT.

Next, in step 134, it is determined whether recording is complete. When the recording is completed, the process returns to step 129.

If it is determined in step 128 that the mode is not automatic, the process returns to step 102.

Note that when the recording switch 5WRE is turned on and the stop switch 5WST is turned on in any mote, the recording switch 5WRE is turned on and the stop switch 5WST is turned on by interrupt processing.

At this time, the changeover switch 102 is connected to the h side, and a through image is displayed on the monitor.

By the way, during playback, the memory 62.6 of the memory means 60
It takes approximately 5 seconds to write one frame worth of video data DSv to the 4.

Therefore, video data DSv and audio data DSa' are recorded on the tape using DAT as shown in FIG. 7A.
In the case where the video data DSv for one frame is written in the memory 62, 64, this one frame worth of video data DSv is repeatedly read out and a still image is displayed on the monitor. Then, the relationship between the reproduced audio and the reproduced image becomes as shown in FIG.

In other words, the image will be displayed approximately 5 seconds after the audio is output, and the reproduction timing of the audio and the image will be significantly different.

In order to improve such timing deviation, memory 6
2. When the writing of one field's worth of video data DSv is completed in 64, until the video data DSv of another one field is written, the first written one field is It is conceivable to repeatedly read out the video data DSv for 30 minutes and display a still image based on a field signal on a monitor. Although not mentioned above, in the signal processing device shown in FIG. 1 as well, a still image based on a field signal is displayed at the start of playback.

When video data DSv and audio data DSa' are recorded in association with each other as shown in FIG. 7A, the relationship between reproduced audio and reproduced image becomes as shown in FIG. 7C.

In other words, the image is displayed approximately 2.5 seconds after the audio is output, and there is still a lag in the playback timing between the audio and the image.

Therefore, in this example, as shown in FIG. 8A, for one frame of video data DSv, one field is recorded, and the corresponding audio data DSa' is recorded from that point onwards. In other words, the controller 100
When the recording of the image data DSv of the odd field is completed, a synchronization signal as shown in FIG. ,Sa
The supply timing of R is controlled.

In addition, depending on the timing of the synchronization signal, the luminescent cord,
For example, the user may be informed of the timing of voice input by lighting an LED.

In this example, the recording timing of the video data DSν and the audio data DSa' is shifted by about one field interval, so the relationship between the reproduced image and the reproduced audio becomes as shown in Figure C. , the playback timings of the image and audio will match.

By the way, in the DAT, the program number for search is recorded in the sub-coat area of the track format (shown in FIG. 9).

The scanning locus of the head during the search (FF search, REW search) spans several tracks, as shown by solid line arrows in FIGS. 10A and 10B. Therefore, for example, during a 200x search, the probability that the head will pass through the subcode area is 9.
This is only three times per second (the recording time of the same program number on the current DAT).

Taking into account that the sub-code can be read without error using a 200x search, it is difficult to shorten the recording time of 9 seconds.

On the other hand, as mentioned above, one frame of video data DS
v is recorded with DAT about 5 seconds ago. Therefore, if a program number is assigned corresponding to approximately 5 seconds in which each frame of video data DSv is recorded, 200
Double search becomes impossible.

Furthermore, if a program number is attached every approximately 5 seconds, a program number of 1400 or more will be required for a 2-hour DAT tape L.

Therefore, program numbers are assigned corresponding to approximately 5 seconds in which each frame of video data DSv is recorded, and in addition to the areas of program numbers 1 to 3,
A four-digit program number is attached using half of the index number area (see back format in FIG. 11).

When a 4-digit program number is attached every approximately 5 seconds, the upper 3 digits of the 4-digit program number are approximately 50 seconds apart. D.A.
The search in T is performed using this fact.

FIG. 12 shows the configuration of the parts involved in the DAT search.

In the figure, a reproduced signal from the head is supplied to a subcode processing circuit 201, and this subcode processing circuit 201
The program number data DPR from is supplied to the CPU 202.

Further, 204 is a capstan motor, and a frequency signal SFG from a frequency generator FG attached to this motor 204 is supplied to a capstan control circuit 203. This control circuit 203 controls the rotation speed and rotation direction of the motor 204. The operation of the control circuit 203 is based on the program number data DPR.
202.

When searching for a certain 4-digit program number,
Utilizing the fact that the upper three digits of the four-digit program number are approximately 50 seconds open and open, the upper three digits are searched by a 200x search. In other words, the subcode processing circuit 201
Until the upper three digits of the program number indicated by the data DPR supplied to the CPU 202 match the target value,
A 200x search is performed.

Next, when the top three digits match the target value, the CPU2
The control circuit 203 is controlled by 02, and a 16 times search is performed. That is, the 16x search is performed until all digits of the program number indicated by the data DPR match the target value.

Fig. 13 shows the operation when searching for program number 1254, in which a 200x search (high speed search) searches for parts 1250 to 1259, and then a 16x search (low speed search) searches for 1254. part is searched.

Note that the 200x and 16x searches are just examples, and the speed is not limited to these as long as the speed is such that the upper three digits and all digits of the program number can be read, respectively.

By the way, by using the signal processing device of the example in FIG. 1, a digital audio signal D Sa can be obtained.

and a digital video signal DSv are mixed and recorded on a DAT using two DATs.
When performing digital dubbing, it is conceivable that the lower 8 bits of the digital video signal DSν are recorded as they are, while the upper 8 bits of the digital audio signal DSa' are replaced with other contents.

FIG. 14 shows a configuration for digital dubbing using two DATs.

In the figure, 301 is the DAT on the master side;
02 is a DAT on the slave side. The digital signal D S m (shown in FIG. 16A, see the second diagram) output from the DAT 301 is supplied as a recording signal to the DAT 302 via the a side of the changeover switch 303, and the bm and dubbing device 304
is supplied to the DAT 302 as a recording signal.

In addition, the pit clock BC output from DAT301
K (shown in FIG. 16C) and a clock LRCK (shown in FIG.
4.

Further, left and right channel audio signals S aL and S sR are supplied to the dubbing device 304 .

FIG. 15 is a diagram showing a specific configuration of the post-recording device 304.

In the figure, the digital signal DSm supplied from the DAT 301 via the changeover switch 303 is supplied to the fixed terminal on the a side of the changeover switch 341.

Clock BCK and LRCK from DAT 301 are supplied to timing generation circuit 343.

Further, the left and right channel audio signals SaL and SaR are supplied to a signal processing circuit 342. This signal processing circuit 3
42 is supplied with the clock LRCK, and is also supplied with a clock of frequency fs from the timing generation circuit 343.

This signal processing circuit 342 is the amplifier 9L in FIG.
, 9R to compression circuit 14, and outputs an 8-bit compressed digital audio signal DSa' (shown in FIG. 16, see FIG. 2B). This digital audio signal DSa' is transferred to the selector switch 34.
It is supplied to the b@ fixed terminal of 1.

Furthermore, the timing generation circuit 343 uses a clock BCK.
, LRCK, the digital signal DSm becomes a low level "0" corresponding to the video signal DSv, and becomes a high level "1" corresponding to the audio signal DSa,
A word clock WCK (shown in FIG. 16E) whose state changes every 8 bit clocks is generated.

The word clock WCK is supplied to the changeover switch 341 as a changeover control signal. The changeover switch 341 is connected to the a side when the clock WCK is at a low level "0", and is connected to the b* side when the clock WCK is at a high level "1".

As a result, the changeover switch 341 outputs a digital signal DSs (shown in FIG.
This results in an output signal of 4.

Returning to FIG. 14, when dubbing, the selector switch 303
When connecting the DAT 301 to the a side, the digital signal DSm output from the DAT 301 is directly supplied to the DAT 302 and recorded.

Furthermore, when the selector switch 303 is connected to the b side during dubbing, the digital signal DSs output from the dubbing device 304 is supplied to the DAT 302 and recorded. In other words, audio dubbing processing is performed.

In the above-mentioned embodiment, the audio signal DSa' is arranged in the upper 8 bits and the video signal DSv is arranged in the lower 8 bits for the total number of bits of 16 for recording and reproduction, but the number of bits and the arrangement position are different. Of course, it is not limited to this.

Further, in the above-described embodiments, the audio signal is compressed and recorded, but the present invention can be similarly applied to audio signals that are recorded without being compressed.

Further, in the above-described embodiments, a magnetic tape is used for recording and reproducing, but a magnetic disk or an optical recording and reproducing device may be used.

[Effects of the Invention] As explained above, according to the present invention, during recording, recording of an audio signal is started after the odd field image data is recorded, and when playback is started, the odd field image data is written to the memory. Since the time axis conversion process is performed when the image is displayed, the playback timing of the image and audio can be made to match.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a signal processing device, FIG. 2 is a diagram showing an example of the format of a digital signal, FIG. 3 is a diagram showing the structure of recording data, and FIG. 4 is an explanatory diagram of sync bit shift processing. Figure 5 is an explanatory diagram of the most significant bit inversion, Figure 6 is a flowchart showing the recording operation, Figures 7 and 8 ζ
Explanatory diagrams of image and audio playback timing, Figures 9 to 1
FIG. 3 is a diagram for explaining the search, and FIGS. 14 to 16 are diagrams for explaining the audio dubbing. 14... Compression circuit 20... Mixing means 36... Separation means 38... Expansion circuit 62,64... Memory means 80... Identification code generator 94... Identification coat detector 201. ...Subcoat processing circuit 202...CPU 203...Capstan control circuit 204...Capstan motor 301.302...DAT 3044 Quantitative Factors DAT Noriichi 1: Related Subcommittee Figure 12

Claims (1)

[Claims] (1) An N-bit (N is an integer) digital audio signal and an M-bit (M is an integer) digital video signal that has been time-base converted using memory are combined and recorded as an N+M-bit digital signal. The video signal is recorded in units of image data for one frame of odd and even fields, and the M-bit digital video signal, which is separated from the N+M-bit digital signal to be reproduced, is subjected to time axis conversion in the memory. At the start of recording, the final image data of the odd field of the one frame of image data is recorded, and then the digital audio signal is recorded, and at the start of playback, the last image data of the one frame of image data is recorded. During the period from when the final image data of the odd field is written to the memory until the final image data of the even field is written, the image data of the odd field is repeatedly read from the memory, and thereafter, the image data of the odd field is read from the memory. A digital signal recording and reproducing method characterized in that one frame of image data is repeatedly read out.