JPH044756U - - Google Patents
Info
- Publication number
- JPH044756U JPH044756U JP4501390U JP4501390U JPH044756U JP H044756 U JPH044756 U JP H044756U JP 4501390 U JP4501390 U JP 4501390U JP 4501390 U JP4501390 U JP 4501390U JP H044756 U JPH044756 U JP H044756U
- Authority
- JP
- Japan
- Prior art keywords
- mounting section
- semiconductor
- evaluation device
- circuit
- forming board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 9
- 238000011156 evaluation Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Description
第１図はこの考案の一実施例による半導体評価
装置の構成を示す側面図である。第２図はこの考
案の他の実施例による半導体評価装置の構成を示
す側面図である。第３図は従来の半導体評価装置
の構成を示す側面図である。
図において、１は温度調節器、２はヒーテイン
グブロツク、３は測定用治具、４はコネクタ取付
治具、５はコネクタ、６，７は誘電体基板、８は
高周波特トランジスタ、９は半導体素子搭載用治
具、１０は誘電体基板搭載用治具、１１は低熱伝
導率基板、１２は高電導率素材膜である。なお、
図中、同一符号は、同一または相当部分を示す。
FIG. 1 is a side view showing the configuration of a semiconductor evaluation device according to an embodiment of this invention. FIG. 2 is a side view showing the configuration of a semiconductor evaluation device according to another embodiment of the invention. FIG. 3 is a side view showing the configuration of a conventional semiconductor evaluation device. In the figure, 1 is a temperature controller, 2 is a heating block, 3 is a measurement jig, 4 is a connector mounting jig, 5 is a connector, 6 and 7 are dielectric substrates, 8 is a high frequency transistor, and 9 is a semiconductor A jig for mounting an element, 10 is a jig for mounting a dielectric substrate, 11 is a low thermal conductivity substrate, and 12 is a high conductivity material film. In addition,
In the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
回路形成用基板搭載部を備えた半導体評価装置に
おいて、前記半導体搭載部と前記回路形成用基板
搭載部の間に、熱伝導率の低い素材からなる熱遮
断部を備えた半導体評価装置。 a semiconductor mounting section; and on both sides of the semiconductor mounting section,
What is claimed is: 1. A semiconductor evaluation device including a circuit-forming board mounting section, the semiconductor evaluation device comprising: a heat cutoff section made of a material with low thermal conductivity between the semiconductor mounting section and the circuit-forming board mounting section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4501390U JPH044756U (en) | 1990-04-26 | 1990-04-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4501390U JPH044756U (en) | 1990-04-26 | 1990-04-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH044756U true JPH044756U (en) | 1992-01-16 |
Family
ID=31558823
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4501390U Pending JPH044756U (en) | 1990-04-26 | 1990-04-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH044756U (en) |
-
1990
- 1990-04-26 JP JP4501390U patent/JPH044756U/ja active Pending
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