JPH0447731U - - Google Patents
Info
- Publication number
- JPH0447731U JPH0447731U JP9089190U JP9089190U JPH0447731U JP H0447731 U JPH0447731 U JP H0447731U JP 9089190 U JP9089190 U JP 9089190U JP 9089190 U JP9089190 U JP 9089190U JP H0447731 U JPH0447731 U JP H0447731U
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- channel mos
- reset signal
- series
- mos transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 2
Description
第１図は、この考案にかかるリセツト信号発生
回路図、第２図ａ〜ｄは、この考案の実施例を説
明する信号波形図、第３図は、従来のリセツト信
号発生回路図、第４図ａ〜ｃは従来のリセツト信
号発生回路の信号波形図である。
１……正の電源ＶＤＤ、２……負の電源ＶＳＳ
、４……ＮチヤネルＭＯＳトランジスタ、５，１
２……ＰチヤネルＭＯＳトランジスタ、６，１３
……コンデンサー、１１……ＣＭＯＳ論理回路。
FIG. 1 is a reset signal generation circuit diagram according to this invention, FIGS. 2a to 2d are signal waveform diagrams explaining an embodiment of this invention, FIG. 3 is a conventional reset signal generation circuit diagram, and FIG. Figures a to c are signal waveform diagrams of a conventional reset signal generating circuit. 1...Positive power supply VDD, 2...Negative power supply VSS
, 4...N channel MOS transistor, 5,1
2...P channel MOS transistor, 6,13
...Capacitor, 11...CMOS logic circuit.
Claims (1)
セツト信号出力回路において、ＰチヤネルＭＯＳ
トランジスタとコンデンサーを直列に正の電源Ｖ
ＤＤと負の電源ＶＳＳ間に接続し、前記Ｐチヤネ
ルＭＯＳトランジスタのゲートに前記正の電源Ｖ
ＤＤと負の電源ＶＳＳ間に直列に接続したＮチヤ
ネルＭＯＳトランジスタと抵抗の接続ノードを入
力したことを特徴とするリセツト信号発生回路。 In the reset signal output circuit that operates when the power is turned on to the CMOS logic circuit, the P channel MOS
Connect the transistor and capacitor in series with the positive power supply V
DD and the negative power supply VSS, and the positive power supply V is connected to the gate of the P channel MOS transistor.
A reset signal generating circuit characterized in that a connection node of an N-channel MOS transistor and a resistor connected in series between DD and a negative power supply VSS is input.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9089190U JPH0447731U (en) | 1990-08-29 | 1990-08-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9089190U JPH0447731U (en) | 1990-08-29 | 1990-08-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0447731U true JPH0447731U (en) | 1992-04-23 |
Family
ID=31826032
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9089190U Pending JPH0447731U (en) | 1990-08-29 | 1990-08-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0447731U (en) |
-
1990
- 1990-08-29 JP JP9089190U patent/JPH0447731U/ja active Pending