JPH0461933U - - Google Patents
Info
- Publication number
- JPH0461933U JPH0461933U JP10371290U JP10371290U JPH0461933U JP H0461933 U JPH0461933 U JP H0461933U JP 10371290 U JP10371290 U JP 10371290U JP 10371290 U JP10371290 U JP 10371290U JP H0461933 U JPH0461933 U JP H0461933U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- mos transistor
- input circuit
- channel mos
- output signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000295 complement effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Description
第１図〜第４図は本考案のそれぞれ第１〜第４
の実施例の回路図、第５図〜第８図は従来のＣＭ
ＯＳ入力回路の第１〜第４の例の回路図である。
ＶＤＤ……電源、ＩＮ１〜ＩＮ８……入力信号
、ＯＵＴ１〜ＯＵＴ８……出力信号、ＲＳＴ……
パワーオンリセツト信号、１……ＣＭＯＳ２段回
路、２ＵＰ，２ＵＮ，２ＤＰ，２ＤＮ……帰還論
理回路、３ＤＰ，３ＵＰ……Ｐチヤネル型ＭＯＳ
トランジスタ、３ＤＮ，３ＵＮ……Ｎチヤネル型
ＭＯＳトランジスタ、Ｉ１〜Ｉ３……インバータ
、ＮＯＲ……ＮＯＲゲート。
Figures 1 to 4 are the first to fourth figures of the present invention, respectively.
The circuit diagram of the embodiment, FIGS. 5 to 8 are the conventional CM
FIG. 4 is a circuit diagram of first to fourth examples of an OS input circuit. VDD...power supply, IN1-IN8...input signal, OUT1-OUT8...output signal, RST...
Power-on reset signal, 1...CMOS two-stage circuit, 2UP, 2UN, 2DP, 2DN...feedback logic circuit, 3DP, 3UP...P channel type MOS
Transistor, 3DN, 3UN...N channel type MOS transistor, I1-I3...Inverter, NOR...NOR gate.
Claims (1)
端子に入力する入力信号と同相の出力信号を出力
するＣＭＯＳ入力回路において、ソース端子とド
レイン端がそれぞれ電源と前記入力回路の入力端
に接続されると共に帰還ゲート端にパワーオンリ
セツト信号および前記出力信号の逆相帰還信号を
入力するプルアツプ用ＰチヤネルＭＯＳトランジ
スタを有することを特徴とするＣＭＯＳ入力回路
。 ２ 請求項１記載の入力回路において、前記プル
アツプ用ＰチヤネルＭＯＳトランジスタの代わり
にプルアツプ用ＮチヤネルＭＯＳトランジスタを
接続すると共に該プルアツプ用ＮチヤネルＭＯＳ
トランジスタの帰還ゲート端に前記パワーオンリ
セツト信号及び前記出力信号の同相信号を入力す
るとを特徴とするＣＭＯＳ入力回路。 ３ 請求項１記載のＣＭＯＳ入力回路において、
前記プルアツプ用ＰチヤネルＭＯＳトランジスタ
を前記入力端と接地電位点間に接続すると共に前
記帰還ゲート端に前記パワーオンリセツト信号の
逆相信号及び前記出力信号の同相出力信号を供給
することを特徴とするＣＭＯＳ入力回路。 ４ 請求項１記載のＣＭＯＳ入力回路において、
前記プルアツプ用ＰチヤネルＭＯＳトランジスタ
の代わりにＮチヤネルＭＯＳトランジスタを前記
入力端と接地電位点に接続すると共に前記Ｎチヤ
ネルＭＯＳトランジスタの帰還ゲート端に前記パ
ワーオンリセツト信号の同相信号及び前記出力信
号の逆相出力信号を供給することを特徴とするＣ
ＭＯＳ入力回路。[Claims for Utility Model Registration] 1. In a CMOS input circuit that has a plurality of complementary MOS transistors and outputs an output signal that is in phase with an input signal input to an input terminal, a source terminal and a drain terminal are connected to the power supply and the input circuit, respectively. 1. A CMOS input circuit comprising a pull-up P-channel MOS transistor connected to an input terminal of the output signal and inputting a power-on reset signal and a negative phase feedback signal of the output signal to a feedback gate terminal. 2. In the input circuit according to claim 1, an N-channel MOS transistor for pull-up is connected in place of the P-channel MOS transistor for pull-up, and the N-channel MOS transistor for pull-up is
A CMOS input circuit characterized in that the power-on reset signal and an in-phase signal of the output signal are input to a feedback gate end of a transistor. 3. In the CMOS input circuit according to claim 1,
The pull-up P-channel MOS transistor is connected between the input terminal and a ground potential point, and an inverse phase signal of the power-on reset signal and an in-phase output signal of the output signal are supplied to the feedback gate terminal. CMOS input circuit. 4. The CMOS input circuit according to claim 1,
An N-channel MOS transistor is connected to the input terminal and the ground potential point instead of the P-channel MOS transistor for pull-up, and the in-phase signal of the power-on reset signal and the output signal are connected to the feedback gate terminal of the N-channel MOS transistor. C, characterized in that it supplies a negative phase output signal.
MOS input circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10371290U JPH0461933U (en) | 1990-10-02 | 1990-10-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10371290U JPH0461933U (en) | 1990-10-02 | 1990-10-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0461933U true JPH0461933U (en) | 1992-05-27 |
Family
ID=31848689
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10371290U Pending JPH0461933U (en) | 1990-10-02 | 1990-10-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0461933U (en) |
-
1990
- 1990-10-02 JP JP10371290U patent/JPH0461933U/ja active Pending
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