JPH0447757U

JPH0447757U -

Info

Publication number: JPH0447757U
Application number: JP9045790U
Authority: JP
Priority date: 1990-08-29
Filing date: 1990-08-29
Publication date: 1992-04-23

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例を示す構成ブロツク
図、第２図はエラー検出タイミング発生手段が発
生するエラー検出要求信号ＴＭ１と、これを受け
たエラー検出アドレス発生手段が発生するアドレ
ス信号を示す図、第３図はエラー検出要求が発生
した時の動作を示すタイムチヤートである。１……マイクロプロセツサ（ＣＰＵ）、２……
ダイナミツク・ランダム・アクセスメモリ（ＤＲ
ＡＭ）、３……エラー検出タイミング発生手段、
４……エラー検出アドレス発生手段、５……アク
セス制御回路、６……マルチプレクサ、７……パ
リテイチエツカ・ジエネレータ、８……バツフア
、９……フリツプフロツプ、１０……エラーアド
レス格納回路。 FIG. 1 is a configuration block diagram showing an embodiment of the present invention, and FIG. 2 shows an error detection request signal TM1 generated by an error detection timing generation means and an address signal generated by an error detection address generation means that receives the signal. The figure shown in FIG. 3 is a time chart showing the operation when an error detection request occurs. 1... Microprocessor (CPU), 2...
Dynamic random access memory (DR)
AM), 3...Error detection timing generation means,
4...Error detection address generation means, 5...Access control circuit, 6...Multiplexer, 7...Parity checker generator, 8...Buffer, 9...Flip-flop, 10...Error address storage circuit.

Claims

[Scope of utility model registration claim] Dynamic random access memory (D
In a memory system using a RAM (RAM), an error detection timing generation means for requesting a read access to the DRAM at the refresh timing of the DRAM, and an error detection address is generated in response to a timing signal from the error detection timing generation means. an error detection address generating means for generating an error detection address; and receiving a DRAM select signal from the microprocessor and a timing signal from the error detection timing generation means, and performing conflict resolution between the access from the microprocessor and the error detection access, and performs DRAM control. an access control circuit that generates an address multiplex signal; a multiplexer that receives the address multiplex signal from the access control circuit, selects an error detection address from a microprocessor or an error detection address generation means, and supplies the selected error detection address to the DRAM; If an error is detected when an error detection address is given to the DRAM via the parity checker generator and the multiplexer connected to the DRAM data bus,
A memory error detection device characterized by comprising an error address storage circuit for storing an error address at which the error has been detected and notifying a microprocessor, and performing a DRAM refresh operation and an error detection operation at the same time. .