JPH0447767U

JPH0447767U -

Info

Publication number: JPH0447767U
Application number: JP8991590U
Authority: JP
Priority date: 1990-08-28
Filing date: 1990-08-28
Publication date: 1992-04-23

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例を示す回路図、第２
図は第１図のクロツク制御部の具体例図、第３図
は第１図及び第２図の動作を説明するタイミング
チヤート、第４図乃至第６図は従来の加算波形の
説明図である。１，２……メモリ、３，４……Ｄ／Ａ変換器、
５……クロツク制御部、８……加算器。 Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is a specific example of the clock control section in Figure 1, Figure 3 is a timing chart explaining the operation of Figures 1 and 2, and Figures 4 to 6 are illustrations of conventional addition waveforms. . 1, 2...memory, 3, 4...D/A converter,
5... Clock control section, 8... Adder.

Claims

[Claims for Utility Model Registration] A first memory in which first waveform data and trigger data are stored; a second memory in which second waveform data is stored; and a first memory that is read from the first memory. a first D/A converter that converts the first waveform data into an analog signal; a second D/A converter that converts the second waveform data read from the second memory into an analog signal; a clock control unit that supplies a clock to the second memory and the second D/A converter for a preset period of time according to trigger data applied from the first memory; and the first D/A converter. A waveform generator comprising: an adder that adds and outputs an analog signal converted and output from a second D/A converter and an analog signal converted and output from a second D/A converter.